CTB The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. 0x40001000 0x00 0x1000 registers Crypto_Engine Crypto Engine interrupt. 27 CTRL Crypto Control Register. 0x00 0xC0000000 RST Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle. 0 1 reset_write write reset Starts reset operation. 1 reset_read read reset_done Reset complete. 0 busy Reset in progress. 1 INTR Interrupt Enable. Generates an interrupt when done or error set. 1 1 dis Disable 0 en Enable 1 SRC Source Select. This bit selects the hash function and CRC generator input source. 2 1 inputFIFO Input FIFO 0 outputFIFO Output FIFO 1 BSO Byte Swap Output. Note. No byte swap will occur if there is not a full word. 4 1 BSI Byte Swap Input. Note. No byte swap will occur if there is not a full word. 5 1 WAIT_EN Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready. 6 1 WAIT_POL Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state. 7 1 activeLo Active Low. 0 activeHi Active High. 1 WRSRC Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled. 8 2 none None. 0 cipherOutput Cipher Output. 1 readFIFO Read FIFO. 2 RDSRC Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator. 10 2 dmaDisabled DMA Disable. 0 dmaOrApb DMA Or APB. 1 rng RNG. 2 FLAG_MODE Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs. 14 1 unres_wr Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags. 0 res_wr Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect. 1 DMADNEMSK DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA. 15 1 not_used DMA_DONE not used in setting CRYPTO_CTRL.DONE bit. 0 used DMA_DONE used in setting CRYPTO_CTRL.DONE bit. 1 DMA_DONE DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation. 24 1 notDone Not Done. 0 done Done. 1 GLS_DONE Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator. 25 1 HSH_DONE Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation. 26 1 CPH_DONE Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation. 27 1 ERR AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block. 29 1 read-only noError No Error. 0 error Error. 1 RDY Ready. Crypto block ready for more data. 30 1 read-only busy Busy. 0 ready Ready. 1 DONE Done. One or more cryptographic calculations complete (logical OR of done flags). 31 1 read-only CIPHER_CTRL Cipher Control Register. 0x04 ENC Encrypt. Select encryption or decryption of input data. 0 1 encrypt Encrypt. 0 decrypt Decrypt. 1 KEY Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag. 1 1 complete No operation/complete. 0 start Start operation. 1 SRC Source of Random key. 2 2 cipherKey User cipher key (0x4000_1060). 0 regFile Key from battery-backed register file (0x4000_5000 to 0x4000_501F). 2 qspiKey_regFile Key from battery-backed register file (0x4000_5020 to 0x4000_502F). 3 CIPHER Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation. 4 3 dis Disabled. 0 aes128 AES 128. 1 aes192 AES 192. 2 aes256 AES 256. 3 des DES. 4 tdes Triple DES. 5 MODE Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes. 8 3 ECB ECB Mode. 0 CBC CBC Mode. 1 CFB CFB (AES only). 2 OFB OFB (AES only). 3 CTR CTR (AES only). 4 HVC H Vector Computation. 11 1 read-only DTYPE GCM/CCM data type. 12 1 read-only CCMM CCM M Parameter. 13 3 read-only CCML CCM L Parameter. 16 3 read-only HASH_CTRL HASH Control Register. 0x08 INIT Initialize. Initializes hash registers with standard constants. 0 1 nop No operation/complete. 0 start Start operation. 1 XOR XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad. 1 1 dis Disable. 0 en Enable. 1 HASH Hash function selection. 2 3 dis Disabled. 0 sha1 SHA-1. 1 sha224 SHA 224. 2 sha256 SHA 256. 3 sha384 SHA 384. 4 sha512 SHA 512. 5 LAST Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash. 5 1 noEffect No Effect. 0 lastMsgData Last Message Data. 1 CRC_CTRL CRC Control Register. 0x0C CRC Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled. 0 1 dis Disable. 0 en Enable. 1 MSB MSB select. This bit selects the order of calculating CRC on data. 1 1 lsbFirst LSB First. 0 msbFirst MSB First. 1 PRNG Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle. 2 1 ENT Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source. 3 1 HAM Hamming Code Enable. Enable hamming code calculation. 4 1 HRST Hamming Reset. Reset Hamming code ECC generator for next block. 5 1 write-only write reset Starts reset operation. 1 DMA_SRC Crypto DMA Source Address. 0x10 ADDR DMA Source Address. 0 32 DMA_DEST Crypto DMA Destination Address. 0x14 ADDR DMA Destination Address. 0 32 DMA_CNT Crypto DMA Byte Count. 0x18 ADDR DMA Byte Address. 0 32 4 4 DIN[%s] Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register. 0x20 write-only DATA Crypto Data Input. Input can be written to this register instead of using DMA. 0 32 4 4 DOUT[%s] Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits. 0x30 read-only DATA Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm. 0 32 CRC_POLY CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. 0x40 0xEDB88320 POLY CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. 0 32 CRC_VAL CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit. 0x44 0xFFFFFFFF VAL CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit. 0 32 HAM_ECC Hamming ECC Register. 0x4C ECC Hamming ECC Value. These bits are the even parity of their corresponding bit groups. 0 16 PAR Parity. This is the parity of the entire array. 16 1 even Even. 0 odd Odd. 1 4 4 CIPHER_INIT[%s] Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. 0x50 IVEC Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. 0 32 8 4 CIPHER_KEY[%s] Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits. 0x60 write-only KEY Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits. 0 32 16 4 HASH_DIGEST[%s] This register holds the calculated hash value. This register is affected by the endian swap bits. 0x80 HASH This register holds the calculated hash value. This register is affected by the endian swap bits. 0 32 4 4 HASH_MSG_SZ[%s] Message Size. This register holds the lowest 32-bit of message size in bytes. 0xC0 MSGSZ Message Size. This register holds the lowest 32-bit of message size in bytes. 0 32 2 4 AAD_LENGTH[%s] AAD Length Registers. 0xD0 0x0 LENGTH AAD length in bytes for AES GCM and CCM operations. 0 32 2 4 PLD_LENGTH[%s] PLD Length Registers. 0xD8 0x0 LENGTH PLD length in bytes for AES GCM and CCM operations. 0 32 4 4 TAGMIC[%s] TAG/MIC Registers. 0xE0 LENGTH TAG/MIC output for AES GCM and CCM operations. 0 32 SCA_CTRL0 SCA Control 0 Register. 0x100 STC Start Calculation. 0 1 SCAIE SCA Interrupt Enable. 1 1 disable Disable 0 enable Enable 1 ABORT Abort Operation. 2 1 ERMEM Erase Cryptographic Memory. 4 1 MANPARAM ECC Parameter Source. 5 1 HWKEY Hardware Key Select. 6 1 OPCODE SCA Opcode. 8 5 MODADDR MODULO Address Offset. 16 5 ECCSIZE ECC Size. 24 2 SCA_CTRL1 SCA Control 1 Register. 0x104 MAN SCA Mode. 0 1 auto Auto Mode 0 manual Manual Mode 1 AUTOCARRY Automatically propagate the carry for the next operation. 1 1 PLUSONE Enable Carry propagation for the next operation. 2 1 NRNG NRNG. 5 1 CARRYPOS To set Carry location. 8 10 SCA_STAT SCA Status Register. 0x108 BUSY SCA Busy. 0 1 SCAIF SCA Interrupt Flag. 1 1 PVF1 Point 1 Verification Failed. 2 1 PVF2 Point 2 Verification Failed. 3 1 FSMERR FSM Transition Error. 4 1 COMPERR EC Computation Error. 5 1 MEMERR SCA Memory Access Error. 6 1 CARRY Carry on ongoing operation. 8 1 GTE2I2 Modulo 2x Result. 9 1 ALUNEG1 ALU 2 SubSign of the subtraction result for ALU_2. 10 1 ALUNEG2 ALU 2 SubSign of the subtraction result for ALU_2. 11 1 SCA_PPX_ADDR PPX Coordinate Data Pointer Register. 0x10C 0x0 ADDR Point P Coordinate Data Pointer. 0 32 SCA_PPY_ADDR PPY Coordinate Data Pointer Register. 0x110 0x0 ADDR Point P Coordinate Data Pointer. 0 32 SCA_PPZ_ADDR PPZ Coordinate Data Pointer Register. 0x114 0x0 ADDR Point P Coordinate Data Pointer. 0 32 SCA_PQX_ADDR PQX Coordinate Data Pointer Register. 0x118 0x0 ADDR Point Q Coordinate Data Pointer. 0 32 SCA_PQY_ADDR PQY Coordinate Data Pointer Register. 0x11C 0x0 ADDR Point Q Coordinate Data Pointer. 0 32 SCA_PQZ_ADDR PQZ Coordinate Data Pointer Register. 0x120 0x0 ADDR Point Q Coordinate Data Pointer. 0 32 SCA_RDSA_ADDR SCA RDSA Address Register. 0x124 0x0 ADDR The starting address of the R portion for R, S ECDSA signature. 0 32 SCA_RES_ADDR SCA Result Address Register. 0x128 0x0 ADDR Starting address of result storage. 0 32 SCA_OP_BUFF_ADDR SCA Operation Buffer Address Register. 0x12C 0x0 ADDR Starting address of operation buffer. 0 32 SCA_MODDATA SCA Modulo Data Input Register. 0x130 0x0 DATA Used to load the SCA modulo for modular operations. 0 32 SCA_NRNG Starting address for NRNG stored in SRAM. 0x134 0x0