CLCD Color LCD Controller 0x40031000 0x00 0x1000 registers CLKCTRL LCD Clock Control Register 0x000 CLKDIV Clock divsor 0 8 ACB ACB 8 8 DPOL D Polarity 16 1 ACTIVEHI Active Hi 0 ACTIVELO Active Low 1 VPOL V Polarity 17 1 ACTIVEHI Active Hi 1 ACTIVELO Active Low 0 HPOL H Polarity 18 1 ACTIVEHI Active Hi 1 ACTIVELO Active Low 0 EDGE Edge Selection 19 1 RISEEDGE Rising edge 0 FALLEDGE Falling Edge 1 PASCLK Clock Active on Data 20 1 ALWAYSACTIVE Always Active 0 ACTIVEONDATA ACTIVE ON DATA 1 VTIM0 LCD Vertical Timing 0 Register 0x004 VLINES V Lines 0 8 VBACKPORCH V BACK PORCH 16 8 VTIM1 LCD Vertical Timing 1 Register 0x008 VSYNCWIDTH V Sync Width 0 8 VFRONTPORCH V Front PORCH 16 8 HTIM LCD Horizontal Timing Register. 0x00C HSYNCWIDTH Horizontal Sync Width in CLCD Clocks from 1 to 256 HSync Width = HSYNCWIDTH+1 Clocks 0 8 HFRONTPORCH Horizontal Front Porch size in lines from 1 to 256 8 8 HSIZE Horizontal Front Porch Size in Pixels = (HSIZE + 1) *16 16 8 HBACKPORCH Horizontal Back Porch size in CLCD Clocks from 1 to 256 -> HBP= (HBACKPORCH+1) 24 8 CTRL LCD Control Register 0x010 EN LCD Enable 0 1 DISABLE Disable 0 ENABLE Enable 1 VISEL VI Select 1 2 ONVERTSYNC On Vertical Sync 0 ONVERTBACKPORCH On Vertical Back Porch 1 ONACTIVEVIDEO On Active Video 2 ONVERTFRONTPORCH On Vertical Front Porch 3 DISPTYPE Display Type 4 4 STNCOLOR8BIT STN Color 8 bit 4 CLCD CLCD 8 BPP BPP 8 3 BPP1 BPP 1 0 BPP2 BPP 2 1 BPP4 BPP 4 2 BPP8 BPP 8 3 BPP16 BPP 16 4 BPP24 BPP 24 5 MODE565 MODE565 11 1 BGR556 MODE 556 0 RGB565 MODE 565 1 EMODE EMODE 12 2 LLBP LLBP 0 BBBP BBBP 1 LBBP LBBP 2 RFU RFU 3 C24 C24 15 1 BURST BURST 19 2 WORDS4 WORDS4 0 WORDS8 WORDS8 1 LPOL LPOL 21 1 ACTIVEHI ACTIVE HIGH 0 ACTIVELO ACTIVE LOW 1 PEN PEN 22 1 2 4 FRBUF[%s] Frame Buffer Address Register. 0x018 ADDR Frame Buffer Address. 0 32 INTEN LCD Interrupt Enable Register. 0x020 UFLO Under FLow Interupt Enable 0 1 ADRRDY Address Ready Interupt Enable 1 1 VCI VCI Interupt Enable 2 1 BERR BERR Interupt Enable 3 1 INTFL LCD Interrupt Status Register. 0x024 oneToClear UFLO Under FLow Interupt Status 0 1 read Inactive No interrupt pending 0 Pending Interrupt pending 1 write Clear Clears the interrupt flag 1 ADRRDY Address Ready Interupt Status 1 1 read Inactive No interrupt pending 0 Pending Interrupt pending 1 write Clear Clears the interrupt flag 1 VCI VCI Interupt Status 2 1 read Inactive No interrupt pending 0 Pending Interrupt pending 1 write Clear Clears the interrupt flag 1 BERR BERR Interupt Status 3 1 read Inactive No interrupt pending 0 Pending Interrupt pending 1 write Clear Clears the interrupt flag 1 LCDIDLE LCD IDLE Staus 8 1 BUSY BUSY 0 READY READY 1 HVPHA LCD PHASE, between HSYNC and VSYNC, Register. 0x030 THV Phase Difference in number of pixel clock. 0 8 256 4 PALETTE[%s] Palette 0x400 RED Red Data for Pallet Entry. 0 8 GREEN Green Data for Pallet Entry. 8 8 BLUE Blue Data for Pallet Entry. 16 8