ADC Inter-Integrated Circuit. ADC 0x40034000 32 0x00 0x1000 registers ADC ADC IRQ 20 CTRL0 Control Register 0. 0x00 ADC_EN ADC Enable. [0:0] read-write dis Disable ADC. 0 en enable ADC. 1 BIAS_EN Bias Enable. [1:1] read-write dis Disable Bias. 0 en Enable Bias. 1 SKIP_CAL Skip Calibration Enable. [2:2] read-write no_skip Do not skip calibration. 0 skip Skip calibration. 1 CHOP_FORCE Chop Force Control. [3:3] read-write dis Do not force chop mode. 0 en Force chop Mode. 1 RESETB Reset ADC. [4:4] read-write reset reset ADC. 0 activate activate ADC. 1 CTRL1 Control Register 1. 0x04 START Start conversion control. [0:0] read-write stop Stop conversions. 0 start Start conversions. 1 TRIG_MODE Trigger mode control. [1:1] read-write software software trigger mode. 0 hardware hardware trigger mode. 1 CNV_MODE Conversion mode control. [2:2] read-write atomic Do one conversion sequence. 0 continuous Do continuous conversion sequences. 1 SAMP_CK_OFF Sample clock off control. [3:3] read-write always Sample clock always generated. 0 cnv_only Sample clock generated only when converting. 1 TRIG_SEL Hardware trigger source select. [6:4] read-write TS_SEL Temp sensor select. [7:7] read-write dis Temp sensor is not one of the slots in the sequence. 0 en Temp sensor is one of the slots in the sequence. 1 AVG Number of samples to average for each output data code. [10:8] read-write avg1 1 Sample per output code. 0 avg2 2 Samples per output code. 1 avg4 4 Samples per output code. 2 avg8 8 Samples per output code. 3 avg16 16 Samples per output code. 4 avg32 32 Samples per output code. 5 NUM_SLOTS Number of slots enabled for the conversion sequence [20:16] read-write CLKCTRL Clock Control Register. 0x08 CLKSEL Clock source select. [1:0] read-write HCLK Select HCLK. 0 CLK_ADC0 Select CLK_ADC0. 1 CLK_ADC1 Select CLK_ADC1. 2 CLK_ADC2 Select CLK_ADC2. 3 CLKDIV Clock divider control. [6:4] read-write DIV2 Divide by 2. 0 DIV4 Divide by 4. 1 DIV8 Divide by 8. 2 DIV16 Divide by 16. 3 DIV1 Divide by 1. 4 SAMPCLKCTRL Sample Clock Control Register. 0x0C read-write TRACK_CNT Number of cycles for SAMPLE_CLK high time. [15:0] read-write IDLE_CNT Number of cycles for SAMPLE_CLK low time. [31:16] read-write CHSEL0 Channel Select Register 0. 0x10 slot0_id channel assignment for slot 0. [4:0] read-write slot1_id channel assignment for slot 1. [12:8] read-write slot2_id channel assignment for slot 2. [20:16] read-write slot3_id channel assignment for slot 3. [28:24] read-write CHSEL1 Channel Select Register 1. 0x14 slot4_id channel assignment for slot 4. [4:0] read-write slot5_id channel assignment for slot 5. [12:8] read-write slot6_id channel assignment for slot 6. [20:16] read-write slot7_id channel assignment for slot 7. [28:24] read-write CHSEL2 Channel Select Register 2. 0x18 slot8_id channel assignment for slot 8. [4:0] read-write slot9_id channel assignment for slot 9. [12:8] read-write slot10_id channel assignment for slot 10. [20:16] read-write slot11_id channel assignment for slot 11. [28:24] read-write CHSEL3 Channel Select Register 3. 0x1C slot12_id channel assignment for slot 12. [4:0] read-write slot13_id channel assignment for slot 13. [12:8] read-write slot14_id channel assignment for slot 14. [20:16] read-write slot15_id channel assignment for slot 15. [28:24] read-write RESTART Restart Count Control Register 0x30 CNT Number of sample periods to skip before restarting a continuous mode sequence [15:0] read-write DATAFMT Channel Data Format Register 0x3C MODE Data format control [31:0] read-write FIFODMACTRL FIFO and DMA control 0x40 DMA_EN DMA Enable. [0:0] read-write dis Disable DMA. 0 en Enable DMA. 1 FLUSH FIFO Flush. [1:1] read-write normal Normal FIFO operation. 0 flush Flush FIFO. 1 DATA_FORMAT DATA format control. [3:2] read-write data_status Data and Status in FIFO. 0 data_only Only Data in FIFO. 1 raw_data_only Only Raw Data in FIFO. 2 THRESH FIFO Threshold. These bits define the FIFO interrupt threshold. [15:8] read-write DATA Data Register (FIFO). 0x44 DATA Conversion data. [15:0] read-only CHAN Channel for the data. [20:16] read-only INVALID Invalid status for the data. [24:24] read-only CLIPPED Clipped status for the data. [31:31] read-only STATUS Status Register 0x48 READY Indication that the ADC is in ON power state [0:0] read-only EMPTY FIFO Empty [1:1] read-only FULL FIFO full [2:2] read-only FIFO_LEVEL Number of entries in FIFO available to read [15:8] read-only CHSTATUS Channel Status 0x4C CLIPPED [31:0] read-write INTEN Interrupt Enable Register. 0x50 READY ADC is ready. [0:0] read-write ABORT Conversion start is aborted. [2:2] read-write START_DET Conversion start is detected. [3:3] read-write SEQ_STARTED [4:4] read-write SEQ_DONE [5:5] read-write CONV_DONE [6:6] read-write CLIPPED [7:7] read-write FIFO_LVL [8:8] read-write FIFO_UFL [9:9] read-write FIFO_OFL [10:10] read-write INTFL Interrupt Flags Register. 0x54 READY ADC is ready. [0:0] read-write oneToClear ABORT Conversion start is aborted. [2:2] read-write oneToClear START_DET Conversion start is detected. [3:3] read-write oneToClear SEQ_STARTED [4:4] read-write oneToClear SEQ_DONE [5:5] read-write oneToClear CONV_DONE [6:6] read-write oneToClear CLIPPED [7:7] read-write oneToClear FIFO_LVL [8:8] read-write oneToClear FIFO_UFL [9:9] read-write oneToClear FIFO_OFL [10:10] read-write oneToClear SFRADDROFFSET SFR Address Offset Register 0x60 OFFSET Address Offset for SAR Digital [7:0] read-write SFRADDR SFR Address Register 0x64 ADDR Address to SAR Digital [7:0] read-write SFRWRDATA SFR Write Data Register 0x68 DATA DATA to SAR Digital [7:0] read-write SFRRDDATA SFR Read Data Register 0x6C DATA DATA from SAR Digital [7:0] read-only SFRSTATUS SFR Status Register 0x70 NACK NACK status for SAR Digital SFR communication [0:0] read-only