Maxim-Integrated Maxim max78000 ARMCM4 1.0 MAX78000 Machine Learning System-on-Chip. CM4 r2p1 little true true 3 false 8 32 0x20 read-write 0x00000000 0xFFFFFFFF ADC 10-bit Analog to Digital Converter 0x40034000 32 read-write 0 0x1000 registers ADC ADC IRQ 20 CTRL ADC Control 0x0000 read-write start Start ADC Conversion [0:0] read-write pwr ADC Power Up [1:1] read-write refbuf_pwr ADC Reference Buffer Power Up [3:3] read-write ref_sel ADC Reference Select [4:4] read-write ref_scale ADC Reference Scale [8:8] read-write scale ADC Scale [9:9] read-write clk_en ADC Clock Enable [11:11] read-write ch_sel ADC Channel Select [16:12] read-write AIN0 0 AIN1 1 AIN2 2 AIN3 3 AIN4 4 AIN5 5 AIN6 6 AIN7 7 VcoreA 8 VcoreB 9 Vrxout 10 Vtxout 11 VddA 12 VddB VddB/4 13 Vddio Vddio/4 14 Vddioh Vddioh/4 15 VregI VregI/4 16 adc_divsel Scales the external inputs, all inputs are scaled the same [18:17] read-write DIV1 0 DIV2 1 DIV3 2 DIV4 3 data_align ADC Data Alignment Select [20:20] read-write STATUS ADC Status 0x0004 read-write active ADC Conversion In Progress [0:0] read-only afe_pwr_up_active AFE Power Up Delay Active [2:2] read-only overflow ADC Overflow [3:3] read-only DATA ADC Output Data 0x0008 read-write adc_data ADC Converted Sample Data Output [15:0] read-only INTR ADC Interrupt Control Register 0x000C read-write done_ie ADC Done Interrupt Enable [0:0] read-write ref_ready_ie ADC Reference Ready Interrupt Enable [1:1] read-write hi_limit_ie ADC Hi Limit Monitor Interrupt Enable [2:2] read-write lo_limit_ie ADC Lo Limit Monitor Interrupt Enable [3:3] read-write overflow_ie ADC Overflow Interrupt Enable [4:4] read-write done_if ADC Done Interrupt Flag [16:16] read-write oneToClear ref_ready_if ADC Reference Ready Interrupt Flag [17:17] read-write oneToClear hi_limit_if ADC Hi Limit Monitor Interrupt Flag [18:18] read-write oneToClear lo_limit_if ADC Lo Limit Monitor Interrupt Flag [19:19] read-write oneToClear overflow_if ADC Overflow Interrupt Flag [20:20] read-write oneToClear pending ADC Interrupt Pending Status [22:22] read-only 4 4 LIMIT[%s] ADC Limit 0x0010 read-write ch_lo_limit Low Limit Threshold [9:0] read-write ch_hi_limit High Limit Threshold [21:12] read-write ch_sel ADC Channel Select [28:24] read-write ch_lo_limit_en Low Limit Monitoring Enable [29:29] read-write ch_hi_limit_en High Limit Monitoring Enable [30:30] read-write AES AES Keys. 0x40007400 0x00 0x400 registers CTRL AES Control Register 0x0000 32 EN AES Enable [0:0] read-write DMA_RX_EN DMA Request To Read Data Output FIFO [1:1] read-write DMA_TX_EN DMA Request To Write Data Input FIFO [2:2] read-write START Start AES Calculation [3:3] read-write INPUT_FLUSH Flush the data input FIFO [4:4] read-write OUTPUT_FLUSH Flush the data output FIFO [5:5] read-write KEY_SIZE Encryption Key Size [7:6] read-write AES128 128 Bits. 0 AES192 192 Bits. 1 AES256 256 Bits. 2 TYPE Encryption Type Selection [9:8] read-write STATUS AES Status Register 0x0004 BUSY AES Busy Status [0:0] read-write INPUT_EM Data input FIFO empty status [1:1] read-write INPUT_FULL Data input FIFO full status [2:2] read-write OUTPUT_EM Data output FIFO empty status [3:3] read-write OUTPUT_FULL Data output FIFO full status [4:4] read-write INTFL AES Interrupt Flag Register 0x0008 DONE AES Done Interrupt [0:0] read-write KEY_CHANGE External AES Key Changed Interrupt [1:1] read-write KEY_ZERO External AES Key Zero Interrupt [2:2] read-write OV Data Output FIFO Overrun Interrupt [3:3] read-write KEY_ONE KEY_ONE [4:4] read-write INTEN AES Interrupt Enable Register 0x000C DONE AES Done Interrupt Enable [0:0] read-write KEY_CHANGE External AES Key Changed Interrupt Enable [1:1] read-write KEY_ZERO External AES Key Zero Interrupt Enable [2:2] read-write OV Data Output FIFO Overrun Interrupt Enable [3:3] read-write KEY_ONE KEY_ONE [4:4] read-write FIFO AES Data Register 0x0010 DATA AES FIFO [0:0] read-write AESKEYS AES Key Registers. 0x40007800 0x00 0x400 registers KEY0 AES Key 0. 0x00 32 KEY1 AES Key 1. 0x04 32 KEY2 AES Key 2. 0x08 32 KEY3 AES Key 3. 0x0C 32 KEY4 AES Key 4. 0x10 32 KEY5 AES Key 5. 0x14 32 KEY6 AES Key 6. 0x18 32 KEY7 AES Key 7. 0x1C 32 CAMERAIF Parallel Camera Interface. 0x4000E000 32 read-write 0 0x1000 registers CameraIF 91 VER Hardware Version. 0x0000 read-write minor Minor Version Number. [7:0] read-write major Major Version Number. [15:8] read-write FIFO_SIZE FIFO Depth. 0x0004 read-write fifo_size FIFO size. [7:0] read-write CTRL Control Register. 0x0008 read-write READ_MODE Read Mode. 0 2 read-write dis Camera Interface Disabled. 0 single_img Single Image Capture. 1 continuous Continuous Image Capture. 2 DATA_WIDTH Data Width. 2 2 read-write 8bit 8 bit. 0 10bit 10 bit. 1 12bit 12 bit. 2 DS_TIMING_EN DS Timing Enable. 4 1 read-write dis Timing from VSYNC and HSYNC. 0 en Timing embedded in data using SAV and EAV codes. 1 FIFO_THRSH Data FIFO Threshold. 5 5 read-write RX_DMA DMA Enable. 16 1 read-write dis DMA disabled. 0 en DMA enabled. 1 RX_DMA_THRSH DMA Threshold. 17 4 read-write THREE_CH_EN Three-channel mode enable. 30 1 read-write PCIF_SYS PCIF Control. 31 1 read-write dis PCIF disabled. 0 en PCIF enabled. 1 INT_EN Interupt Enable Register. 0x000C read-write IMG_DONE Image Done. 0 1 read-write FIFO_FULL FIFO Full. 1 1 read-write FIFO_THRESH FIFO Threshold Level Met. 2 1 read-write FIFO_NOT_EMPTY FIFO Not Empty. 3 1 read-write INT_FL Interupt Flag Register. 0x0010 read-write IMG_DONE Image Done. 0 1 read-write FIFO_FULL FIFO Full. 1 1 read-write FIFO_THRESH FIFO Threshold Level Met. 2 1 read-write FIFO_NOT_EMPTY FIFO Not Empty. 3 1 read-write DS_TIMING_CODES DS Timing Code Register. 0x0014 read-write SAV Start Active Video Code. [7:0] read-write EAV End Active Video Code. [15:8] read-write FIFO_DATA FIFO DATA Register. 0x0030 read-write DATA Data from FIFO to be read by DMA. [31:0] read-write CRC CRC Registers. 0x4000F000 0x00 0x1000 registers CTRL CRC Control 0x0000 32 EN CRC Enable [0:0] read-write DMA_EN DMA Request Enable [1:1] read-write MSB MSB Select [2:2] read-write BYTE_SWAP_IN Byte Swap CRC Data Input [3:3] read-write BYTE_SWAP_OUT Byte Swap CRC Value Output [4:4] read-write BUSY CRC Busy [16:16] read-write DATAIN32 CRC Data Input 0x0004 DATA CRC Data [31:0] read-write 2 2 DATAIN16[%s] CRC Data Input 0x0004 16 read-write DATA CRC Data 0 16 read-write 4 1 DATAIN8[%s] CRC Data Input 0x0004 8 read-write DATA CRC Data 0 8 read-write POLY CRC Polynomial 0x0008 POLY CRC Polynomial [31:0] read-write VAL Current CRC Value 0x000C VALUE Current CRC Value [31:0] read-write DMA DMA Controller Fully programmable, chaining capable DMA channels. 0x40028000 32 0x00 0x1000 registers DMA0 28 DMA1 45 DMA2 46 DMA3 47 INTEN DMA Control Register. 0x000 CH0 Channel 0 Interrupt Enable. 0 1 dis Disable. 0 en Enable. 1 CH1 Channel 1 Interrupt Enable. 1 1 CH2 Channel 2 Interrupt Enable. 2 1 CH3 Channel 3 Interrupt Enable. 3 1 INTFL DMA Interrupt Register. 0x004 read-only CH0 Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CH1 1 1 CH2 2 1 CH3 3 1 4 0x20 CH[%s] DMA Channel registers. dma_ch 0x100 read-write CTRL DMA Channel Control Register. 0x000 EN Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 RLDEN Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. 1 1 dis Disable. 0 en Enable. 1 PRI DMA Priority. 2 2 high Highest Priority. 0 medHigh Medium High Priority. 1 medLow Medium Low Priority. 2 low Lowest Priority. 3 REQUEST Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. 4 6 MEMTOMEM Memory To Memory 0x00 SPI1RX SPI1 RX 0x01 UART0RX UART0 RX 0x04 UART1RX UART1 RX 0x05 I2C0RX I2C0 RX 0x07 I2C1RX I2C1 RX 0x08 ADC ADC 0x09 I2C2RX I2C2 RX 0x0A UART2RX UART2 RX 0x0E SPI0RX SPI0 RX 0x0F AESRX AES RX 0x10 UART3RX UART3 RX 0x1C I2SRX I2S RX 0x1E SPI1TX SPI1 TX 0x21 UART0TX UART0 TX 0x24 UART1TX UART1 TX 0x25 I2C0TX I2C0 TX 0x27 I2C1TX I2C1 TX 0x28 I2C2TX I2C2 TX 0x2A CRCTX CRC TX 0x2C PCIFTX PCIF TX 0x2D UART2TX UART2 TX 0x2E SPI0TX SPI0 TX 0x2F AESTX AES TX 0x30 UART3TX UART3 TX 0x3C I2STX I2S TX 0x3E TO_WAIT Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. 10 1 dis Disable. 0 en Enable. 1 TO_PER Timeout Period Select. 11 3 to4 Timeout of 3 to 4 prescale clocks. 0 to8 Timeout of 7 to 8 prescale clocks. 1 to16 Timeout of 15 to 16 prescale clocks. 2 to32 Timeout of 31 to 32 prescale clocks. 3 to64 Timeout of 63 to 64 prescale clocks. 4 to128 Timeout of 127 to 128 prescale clocks. 5 to256 Timeout of 255 to 256 prescale clocks. 6 to512 Timeout of 511 to 512 prescale clocks. 7 TO_CLKDIV Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. 14 2 dis Disable timer. 0 div256 hclk / 256. 1 div64k hclk / 64k. 2 div16M hclk / 16M. 3 SRCWD Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. 16 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 SRCINC Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. 18 1 dis Disable. 0 en Enable. 1 DSTWD Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). 20 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 DSTINC Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. 22 1 dis Disable. 0 en Enable. 1 BURST_SIZE Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. 24 5 DIS_IE Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. 30 1 dis Disable. 0 en Enable. 1 CTZ_IE Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. 31 1 dis Disable. 0 en Enable. 1 STATUS DMA Channel Status Register. 0x004 STATUS Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). 0 1 read-only dis Disable. 0 en Enable. 1 IPEND Channel Interrupt. 1 1 read-only inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CTZ_IF Count-to-Zero (CTZ) Interrupt Flag 2 1 oneToClear RLD_IF Reload Event Interrupt Flag. 3 1 oneToClear BUS_ERR Bus Error. Indicates that an AHB abort was received and the channel has been disabled. 4 1 oneToClear TO_IF Time-Out Event Interrupt Flag. 6 1 oneToClear SRC Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. 0x008 ADDR 0 32 DST Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. 0x00C ADDR 0 32 CNT DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. 0x010 CNT DMA Counter. 0 24 SRCRLD Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. 0x014 ADDR Source Address Reload Value. 0 31 DSTRLD Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. 0x018 ADDR Destination Address Reload Value. 0 31 CNTRLD DMA Channel Count Reload Register. 0x01C CNT Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. 0 24 EN Count Reload Enable. 31 1 DVS Dynamic Voltage Scaling DVS_ 0x40003C00 0x00 0x0030 registers DVS Dynamic Voltage Scaling Interrupt 83 CTL Control Register 0x00 MON_ENA Enable the DVS monitoring circuit 0 1 ADJ_ENA Enable the power supply adjustment based on measurements 1 1 PS_FB_DIS Power Supply Feedback Disable 2 1 CTRL_TAP_ENA Use the TAP Select for automatic adjustment or monitoring 3 1 PROP_DLY Additional delay to monitor lines 4 2 MON_ONESHOT Measure delay once 6 1 GO_DIRECT Operate in automatic mode or move directly 7 1 DIRECT_REG Step incrementally to target voltage 8 1 PRIME_ENA Include a delay line priming signal before monitoring 9 1 LIMIT_IE Enable Limit Error Interrupt 10 1 RANGE_IE Enable Range Error Interrupt 11 1 ADJ_IE Enable Adjustment Error Interrupt 12 1 REF_SEL Select TAP used for voltage adjustment 13 4 INC_VAL Step size to increment voltage when in automatic mode 17 3 DVS_PS_APB_DIS Prevent the application code from adjusting Vcore 20 1 DVS_HI_RANGE_ANY Any high range signal from a delay line will cause a voltage adjustment 21 1 FB_TO_IE Enable Voltage Adjustment Timeout Interrupt 22 1 FC_LV_IE Enable Low Voltage Interrupt 23 1 PD_ACK_ENA Prevent DVS from ack'ing a request to enter a low power mode until in the idle state 24 1 ADJ_ABORT Causes the DVS to enter the idle state immediately on a request to enter a low power mode 25 1 STAT Status Fields 0x04 0x00000000 DVS_STATE State machine state 0 4 ADJ_UP_ENA DVS Raising voltage 4 1 ADJ_DWN_ENA DVS Lowering voltage 5 1 ADJ_ACTIVE Adjustment to a Direct Voltage 6 1 CTR_TAP_OK Tap Enabled and the Tap is withing Hi/Low limits 7 1 CTR_TAP_SEL Status of selected center tap delay line detect output 8 1 SLOW_TRIP_DET Provides the current combined status of all selected Low Range delay lines 9 1 FAST_TRIP_DET Provides the current combined status of all selected High Range delay lines 10 1 PS_IN_RANGE Indicates if the power supply is in range 11 1 PS_VCNTR Voltage Count value sent to the power supply 12 7 MON_DLY_OK Indicates the monitor delay count is at 0 19 1 ADJ_DLY_OK Indicates the adjustment delay count is at 0 20 1 LO_LIMIT_DET Power supply voltage counter is at low limit 21 1 HI_LIMIT_DET Power supply voltage counter is at high limit 22 1 VALID_TAP At least one delay line has been enabled 23 1 LIMIT_ERR Interrupt flag that indicates a voltage count is at/beyond manufacturer limits 24 1 RANGE_ERR Interrupt flag that indicates a tap has an invalid value 25 1 ADJ_ERR Interrupt flag that indicates up and down adjustment requested simultaneously 26 1 REF_SEL_ERR Indicates the ref select register bit is out of range 27 1 FB_TO_ERR Interrupt flag that indicates a timeout while adjusting the voltage 28 1 FB_TO_ERR_S Interrupt flag that mirror FB_TO_ERR and is write one clear 29 1 FC_LV_DET_INT Interrupt flag that indicates the power supply voltage requested is below the low threshold 30 1 FC_LV_DET_S Interrupt flag that mirrors FC_LV_DET_INT 31 1 DIRECT Direct control of target voltage 0x08 VOLTAGE Sets the target power supply value 0 7 MON Monitor Delay 0x00C DLY Number of prescaled clocks between delay line samples 0 24 PRE Number of clocks before DVS_MON_DLY is decremented 24 8 ADJ_UP Up Delay Register 0x010 DLY Number of prescaled clocks between updates of the adjustment delay counter 0 16 PRE Number of clocks before DVS_ADJ_UP_DLY is decremented 16 8 ADJ_DWN Down Delay Register 0x014 DLY Number of prescaled clocks between updates of the adjustment delay counter 0 16 PRE Number of clocks before DVS_ADJ_DWN_DLY is decremented 16 8 THRES_CMP Up Delay Register 0x018 VCNTR_THRES_CNT Value used to determine 'low voltage' range 0 7 VCNTR_THRES_MASK Mask applied to threshold and vcount to determine if the device is in a low voltage range 8 7 5 4 TAP_SEL[%s] DVS Tap Select Register 0x1C LO Select delay line tap for lower bound of auto adjustment 0 5 LO_TAP_STAT Returns last delay line tap value 5 1 CTR_TAP_STAT Returns last delay line tap value 6 1 HI_TAP_STAT Returns last delay line tap value 7 1 HI Selects delay line tap for high point of auto adjustment 8 5 CTR Selects delay line tap for center point of auto adjustment 16 5 COARSE Selects delay line tap for coarse or fixed delay portion of the line 24 3 DET_DLY Number of HCLK between delay line launch and sampling 29 2 DELAY_ACT Set if the delay is active 31 1 FCR Function Control Register. 0x40000800 0x00 0x400 registers FCTRL0 Function Control 0. 0x00 read-write I2C0DGEN0 I2C0 SDA Pad Deglitcher enable. 20 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C0DGEN1 I2C0 SCL Pad Deglitcher enable. 21 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C1DGEN0 I2C1 SDA Pad Deglitcher enable. 22 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C1DGEN1 I2C1 SCL Pad Deglitcher enable. 23 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C2DGEN0 I2C2 SDA Pad Deglitcher enable. 24 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 I2C2DGEN1 I2C2 SCL Pad Deglitcher enable. 25 1 dis Deglitcher disabled. 0 en Deglitcher enabled. 1 AUTOCAL0 Automatic Calibration 0. 0x04 read-write ACEN Auto-calibration Enable. 0 1 dis Disabled. 0 en Enabled. 1 ACRUN Autocalibration Run. 1 1 not Not Running. 0 run Running. 1 LDTRM Load Trim. 2 1 GAININV Invert Gain. 3 1 not Not Running. 0 run Running. 1 ATOMIC Atomic mode. 4 1 not Not Running. 0 run Running. 1 MU MU value. 8 12 HIRC96MACTMROUT HIRC96M Trim Value. 23 9 AUTOCAL1 Automatic Calibration 1. 0x08 read-write INITTRM Initial Trim Setting. 0 9 AUTOCAL2 Automatic Calibration 2 0x0C read-write DONECNT Auto-callibration Done Counter Setting. 0 8 ACDIV Auto-callibration Div Setting. 8 13 URVBOOTADDR RISC-V Boot Address. 0x10 read-write URVCTRL RISC-V Control Register. 0x14 read-write MEMSEL RAM2, RAM3 exclusive ownership. 0 1 IFLUSHEN URV instruction flush enable. 1 1 FLC Flash Memory Control. FLSH_ 0x40029000 0x00 0x1000 registers Flash_Controller Flash Controller interrupt. 23 ADDR Flash Write Address. 0x00 ADDR Address for next operation. 0 32 CLKDIV Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. 0x04 0x00000064 CLKDIV Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. 0 8 CTRL Flash Control Register. 0x08 WR Write. This bit is automatically cleared after the operation. 0 1 complete No operation/complete. 0 start Start operation. 1 ME Mass Erase. This bit is automatically cleared after the operation. 1 1 PGE Page Erase. This bit is automatically cleared after the operation. 2 1 ERASE_CODE Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. 8 8 nop No operation. 0 erasePage Enable Page Erase. 0x55 eraseAll Enable Mass Erase. The debug port must be enabled. 0xAA PEND Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. 24 1 read-only idle Idle. 0 busy Busy. 1 LVE Low Voltage enable. 25 1 UNLOCK Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. 28 4 unlocked Flash Unlocked. 2 locked Flash Locked. 3 INTR Flash Interrupt Register. 0x024 DONE Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 AF Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. 1 1 noError No Failure. 0 error Failure occurs. 1 DONEIE Flash Done Interrupt Enable. 8 1 disable Disable. 0 enable Enable. 1 AFIE 9 1 ECCDATA ECC Data Register. 0x28 EVEN Error Correction Code Odd Data. 0 9 ODD Error Correction Code Even Data. 16 9 4 4 DATA[%s] Flash Write Data. 0x30 DATA Data next operation. 0 32 ACTRL Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. 0x40 write-only ACTRL Access control. 0 32 WELR0 WELR0 0x80 WELR0 Access control. 0 32 WELR1 WELR1 0x88 WELR1 Access control. 0 32 RLR0 RLR0 0x90 RLR0 Access control. 0 32 RLR1 RLR1 0x98 RLR1 Access control. 0 32 GCR Global Control Registers. 0x40000000 0 0x400 registers SYSCTRL System Control. 0x00 0xFFFFFFFE BSTAPEN Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE. 1 1 FLASH_PAGE_FLIP Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 4 1 normal Physical layout matches logical layout. 0 swapped Bottom half mapped to logical top half and vice versa. 1 ICC0_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 ROMDONE ROM_DONE status. Used to disable SWD interface during system initialization procedure 12 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 SWD_DIS Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set). 14 1 CHKRES ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 OVR Operating Voltage Range. 16 2 RST0 Reset. 0x04 DMA DMA Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT0 Watchdog Timer 0 Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 TMR0 Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TMR1 Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TMR2 Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TMR3 Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 UART0 UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI1 SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 13 1 I2C0 I2C 0 Reset. 16 1 RTC Real Time Clock Reset. 17 1 SMPHR Semaphore Reset. 22 1 TRNG TRNG Reset. This reset is only available during the manufacture testing phase. 24 1 CNN CNN Reset. 25 1 ADC ADC Reset. 26 1 UART2 UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. 28 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCTRL Clock Control. 0x08 0x00000008 SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSCLK_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 ISO The internal 60 MHz oscillator is used for the system clock. 0 INRO 8 kHz LIRC is used for the system clock. 3 IPO The internal 100 MHz oscillator is used for the system clock. 4 IBRO The internal 7.3725 MHz oscillator is used for the system clock. 5 ERTCO 32 kHz is used for the system clock. 6 EXTCLK External clock on GPIO0.30. 7 SYSCLK_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 ERTCO_EN 32 kHz Crystal Oscillator Enable. 17 1 dis Is Disabled. 0 en Is Enabled. 1 ISO_EN 60 MHz High Frequency Internal Reference Clock Enable. 18 1 IPO_EN 100 MHz High Frequency Internal Reference Clock Enable. 19 1 IBRO_EN 7.3725 MHz High Frequency Internal Reference Clock Enable. 20 1 IBRO_VS 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO. 21 1 Vcor VCore Supply 0 1V Dedicated 1V regulated supply. 1 ERTCO_RDY 32 kHz Crystal Oscillator Ready 25 1 read-only not Is not Ready. 0 ready Is Ready. 1 ISO_RDY 60 MHz HIRC Ready. 26 1 IPO_RDY 100 MHz HIRC Ready. 27 1 IBRO_RDY 7.3725 MHz HIRC Ready. 28 1 INRO_RDY 8 kHz Low Frequency Reference Clock Ready. 29 1 PM Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 4 active Active Mode. 0 sleep Cortex-M4 Active, RISC-V Sleep Mode. 1 standby Standby Mode. 2 backup Backup Mode. 4 lpm LPM or CM4 Deep Sleep Mode. 8 upm UPM. 9 powerdown Power Down Mode. 10 GPIO_WE GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTC_WE RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 WUT_WE WUT Wake Up Enable. This bit enables the Wake-Up Timer as wakeup source. 7 1 AINCOMP_WE AIN COMP Wake Up Enable. This bit enables AIN COMP as wakeup source. 9 1 ISO_PD 60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode. 15 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 IPO_PD 100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. 16 1 IBRO_PD 7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. 17 1 PCLKDIV Peripheral Clock Divider. 0x18 0x00000001 ADCFRQ ADC clock Frequency. These bits define the ADC clock frequency. fADC = fPCLK / (ADCFRQ) 10 4 CNNCLKDIV CNN Clock Divider. 14 3 div2 0 div4 1 div8 2 div16 3 div1 4 CNNCLKSEL CNN Clock Select. 17 1 PCLK 0 ISO 1 PCLKDIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Clock Disable. 1 1 DMA DMA Clock Disable. 5 1 SPI1 SPI 1 Clock Disable. 6 1 UART0 UART 0 Clock Disable. 9 1 UART1 UART 1 Clock Disable. 10 1 I2C0 I2C 0 Clock Disable. 13 1 TMR0 Timer 0 Clock Disable. 15 1 TMR1 Timer 1 Clock Disable. 16 1 TMR2 Timer 2 Clock Disable. 17 1 TMR3 Timer 3 Clock Disable. 18 1 ADC ADC Clock Disable. 23 1 CNN CNN Clock Disable. 25 1 I2C1 I2C 1 Clock Disable. 28 1 PT Pluse Train Clock Disable. 29 1 MEMCTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 SYSRAM0ECC SYSRAM0 ECC Select. 16 1 MEMZ Memory Zeroize Control. 0x2C RAM0 System RAM Block 0 Zeroization. 0 1 nop No operation/complete. 0 start Start operation. 1 RAM1 System RAM Block 1 Zeroization. 1 1 RAM2 System RAM Block 2 Zeroization. 2 1 RAM3 System RAM Block 3 Zeroization. 3 1 SYSRAM0ECC System RAM 0 ECC Zeroization. 4 1 ICC0 Instruction Cachei 0 Zeroization. 5 1 ICC1 Instruction Cachei 1 Zeroization. 6 1 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset_read read reset_done Reset complete. 0 busy Starts reset or indicates reset in progress. 1 PT PT Reset. 1 1 OWM OWM Reset. 7 1 CRC CRC Reset. 9 1 AES AES Reset. 10 1 SPI0 SPI 0 Reset. 11 1 SMPHR SMPHR Reset. 16 1 I2S I2S Reset. 19 1 I2C2 I2C2 Reset. 20 1 DVS DVS Reset. 24 1 SIMO SIMO Reset. 25 1 CPU1 CPU1 Reset. 31 1 PCLKDIS1 Peripheral Clock Disable. 0x48 UART2 UART2 Clock Disable. 1 1 en Enable. 0 dis Disable. 1 TRNG TRNG Clock Disable. 2 1 SMPHR SMPHR Clock Disable. 9 1 OWM One-Wire Clock Disable. 13 1 CRC CRC Clock Disable. 14 1 AES AES Clock Disable. 15 1 SPI0 SPI 0 Clock Disable. 16 1 PCIF Parallel Camera Interface Clock Disable. 18 1 I2S I2S Clock Disable. 23 1 I2C2 I2C2 Clock Disable. 24 1 WDT0 Watch Dog Timer 0 Clock Disable. 27 1 CPU1 CPU1 Clock Disable. 31 1 EVENTEN Event Enable Register. 0x4C DMA Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 RX Enable RXEV pin event. When this bit is set, a logic high of GPIO1.8 will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 TX Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9. 2 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSIE System Status Interrupt Enable Register. 0x54 ICEUNLOCK ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 ECCERR ECC Error Register 0x64 RAM ECC System RAM0 Error Flag. Write 1 to clear. 0 1 ECCCED ECC Not Double Error Detect Register 0x68 RAM ECC System RAM0 Error Flag. Write 1 to clear. 0 1 ECCIE ECC IRQ Enable Register 0x6C RAM ECC System RAM0 Error Interrup Enable 0 1 ECCADDR ECC Error Address Register 0x70 ECCERRAD ECC Error Address. 0 32 GPR General Purpose Register. 0x80 GCFR Global Control Function Register. 0x40005800 0x00 0x400 registers REG0 Register 0. 0x00 read-write cnnx16_0_pwr_en CNNx16_0 Power Domain Enable 0 1 cnnx16_1_pwr_en CNNx16_1 Power Domain Enable 1 1 cnnx16_2_pwr_en CNNx16_2 Power Domain Enable 2 1 cnnx16_3_pwr_en CNNx16_3 Power Domain Enable 3 1 REG1 Register 1. 0x04 read-write cnnx16_0_ram_en CNNx16_0 RAM Power Enable 0 1 cnnx16_1_ram_en CNNx16_1 RAM Power Enable 1 1 cnnx16_2_ram_en CNNx16_2 RAM Power Enable 2 1 cnnx16_3_ram_en CNNx16_3 RAM Power Enable 3 1 REG2 Register 2. 0x08 read-write cnnx16_0_iso CNNx16_0 Power Domain Isolation 0 1 cnnx16_1_iso CNNx16_1 Power Domain Isolation 1 1 cnnx16_2_iso CNNx16_2 Power Domain Isolation 2 1 cnnx16_3_iso CNNx16_3 Power Domain Isolation 3 1 REG3 Register 3. 0x0C read-write cnnx16_0_rst CNNx16_0 Power Domain Reset 0 1 cnnx16_1_rst CNNx16_1 Power Domain Reset 1 1 cnnx16_2_rst CNNx16_2 Power Domain Reset 2 1 cnnx16_3_rst CNNx16_3 Power Domain Reset 3 1 GPIO0 Individual I/O for each GPIO GPIO 0x40008000 0x00 0x1000 registers GPIO0 GPIO0 interrupt. 24 EN0 GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. 0x00 GPIO_EN Mask of all of the pins on the port. 0 32 ALTERNATE Alternate function enabled. 0 GPIO GPIO function is enabled. 1 EN0_SET GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. 0x04 ALL Mask of all of the pins on the port. 0 32 EN0_CLR GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. 0x08 ALL Mask of all of the pins on the port. 0 32 OUTEN GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. 0x0C EN Mask of all of the pins on the port. 0 32 dis GPIO Output Disable 0 en GPIO Output Enable 1 OUTEN_SET GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. 0x10 ALL Mask of all of the pins on the port. 0 32 OUTEN_CLR GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. 0x14 ALL Mask of all of the pins on the port. 0 32 OUT GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. 0x18 GPIO_OUT Mask of all of the pins on the port. 0 32 low Drive Logic 0 (low) on GPIO output. 0 high Drive logic 1 (high) on GPIO output. 1 OUT_SET GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. 0x1C write-only GPIO_OUT_SET Mask of all of the pins on the port. 0 32 no No Effect. 0 set Set GPIO_OUT bit in this position to '1' 1 OUT_CLR GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. 0x20 write-only GPIO_OUT_CLR Mask of all of the pins on the port. 0 32 IN GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. 0x24 read-only GPIO_IN Mask of all of the pins on the port. 0 32 INTMODE GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. 0x28 GPIO_INTMODE Mask of all of the pins on the port. 0 32 level Interrupts for this pin are level triggered. 0 edge Interrupts for this pin are edge triggered. 1 INTPOL GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. 0x2C GPIO_INTPOL Mask of all of the pins on the port. 0 32 falling Interrupts are latched on a falling edge or low level condition for this pin. 0 rising Interrupts are latched on a rising edge or high condition for this pin. 1 INEN GPIO Input Enable 0x30 INTEN GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. 0x34 GPIO_INTEN Mask of all of the pins on the port. 0 32 dis Interrupts are disabled for this GPIO pin. 0 en Interrupts are enabled for this GPIO pin. 1 INTEN_SET GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. 0x38 GPIO_INTEN_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set GPIO_INT_EN bit in this position to '1' 1 INTEN_CLR GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. 0x3C GPIO_INTEN_CLR Mask of all of the pins on the port. 0 32 no No Effect. 0 clear Clear GPIO_INT_EN bit in this position to '0' 1 INTFL GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. 0x40 read-only GPIO_INTFL Mask of all of the pins on the port. 0 32 no No Interrupt is pending on this GPIO pin. 0 pending An Interrupt is pending on this GPIO pin. 1 INTFL_CLR GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. 0x48 ALL Mask of all of the pins on the port. 0 32 WKEN GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. 0x4C GPIO_WKEN Mask of all of the pins on the port. 0 32 dis PMU wakeup for this GPIO is disabled. 0 en PMU wakeup for this GPIO is enabled. 1 WKEN_SET GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. 0x50 ALL Mask of all of the pins on the port. 0 32 WKEN_CLR GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. 0x54 ALL Mask of all of the pins on the port. 0 32 DUALEDGE GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. 0x5C GPIO_DUALEDGE Mask of all of the pins on the port. 0 32 no No Effect. 0 en Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. 1 PADCTRL0 GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x60 GPIO_PADCTRL0 The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Weak pull-up mode. 1 pd weak pull-down mode. 2 PADCTRL1 GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x64 GPIO_PADCTRL1 The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Weak pull-up mode. 1 pd weak pull-down mode. 2 EN1 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x68 GPIO_EN1 Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 EN1_SET GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. 0x6C ALL Mask of all of the pins on the port. 0 32 EN1_CLR GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. 0x70 ALL Mask of all of the pins on the port. 0 32 EN2 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x74 GPIO_EN2 Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 EN2_SET GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. 0x78 ALL Mask of all of the pins on the port. 0 32 EN2_CLR GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. 0x7C ALL Mask of all of the pins on the port. 0 32 HYSEN GPIO Input Hysteresis Enable. 0xA8 GPIO_HYSEN Mask of all of the pins on the port. 0 32 SRSEL GPIO Slew Rate Enable Register. 0xAC GPIO_SRSEL Mask of all of the pins on the port. 0 32 FAST Fast Slew Rate selected. 0 SLOW Slow Slew Rate selected. 1 DS0 GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. 0xB0 GPIO_DS0 Mask of all of the pins on the port. 0 32 ld GPIO port pin is in low-drive mode. 0 hd GPIO port pin is in high-drive mode. 1 DS1 GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. 0xB4 GPIO_DS1 Mask of all of the pins on the port. 0 32 PS GPIO Pull Select Mode. 0xB8 ALL Mask of all of the pins on the port. 0 32 VSSEL GPIO Voltage Select. 0xC0 ALL Mask of all of the pins on the port. 0 32 GPIO1 Individual I/O for each GPIO 1 0x40009000 GPIO1 GPIO1 IRQ 25 GPIO2 Individual I/O for each GPIO 2 0x40080400 GPIO2 GPIO2 IRQ 26 I2C0 Inter-Integrated Circuit. I2C 0x4001D000 32 0x00 0x1000 registers I2C0 I2C0 IRQ 13 CTRL Control Register0. 0x00 EN I2C Enable. [0:0] read-write dis Disable I2C. 0 en enable I2C. 1 MST_MODE Master Mode Enable. [1:1] read-write slave_mode Slave Mode. 0 master_mode Master Mode. 1 GC_ADDR_EN General Call Address Enable. [2:2] read-write dis Ignore Gneral Call Address. 0 en Acknowledge general call address. 1 IRXM_EN Interactive Receive Mode. [3:3] read-write dis Disable Interactive Receive Mode. 0 en Enable Interactive Receive Mode. 1 IRXM_ACK Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. [4:4] read-write ack return ACK (pulling SDA LOW). 0 nack return NACK (leaving SDA HIGH). 1 SCL_OUT SCL Output. This bits control SCL output when SWOE =1. [6:6] read-write drive_scl_low Drive SCL low. 0 release_scl Release SCL. 1 SDA_OUT SDA Output. This bits control SDA output when SWOE = 1. [7:7] read-write drive_sda_low Drive SDA low. 0 release_sda Release SDA. 1 SCL SCL status. This bit reflects the logic gate of SCL signal. [8:8] read-only SDA SDA status. THis bit reflects the logic gate of SDA signal. [9:9] read-only BB_MODE Software Output Enable. [10:10] read-write outputs_disable I2C Outputs SCLO and SDAO disabled. 0 outputs_enable I2C Outputs SCLO and SDAO enabled. 1 READ Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. [11:11] read-only write Write. 0 read Read. 1 CLKSTR_DIS This bit will disable slave clock stretching when set. [12:12] read-write en Slave clock stretching enabled. 0 dis Slave clock stretching disabled. 1 ONE_MST_MODE SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. [13:13] read-write dis Standard open-drain operation: drive low for 0, Hi-Z for 1 0 en Non-standard push-pull operation: drive low for 0, drive high for 1 1 HS_EN High speed mode enable [15:15] read-write STATUS Status Register. 0x04 BUSY Bus Status. [0:0] read-only idle I2C Bus Idle. 0 busy I2C Bus Busy. 1 RX_EM RX empty. [1:1] read-only not_empty Not Empty. 0 empty Empty. 1 RX_FULL RX Full. [2:2] read-only not_full Not Full. 0 full Full. 1 TX_EM TX Empty. [3:3] not_empty Not Empty. 0 empty Empty. 1 TX_FULL TX Full. [4:4] not_empty Not Empty. 0 empty Empty. 1 MST_BUSY Clock Mode. [5:5] read-only not_actively_driving_scl_clock Device not actively driving SCL clock cycles. 0 actively_driving_scl_clock Device operating as master and actively driving SCL clock cycles. 1 INTFL0 Interrupt Status Register. 0x08 DONE Transfer Done Interrupt. [0:0] INT_FL0_Done inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 IRXM Interactive Receive Interrupt. [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 GC_ADDR_MATCH Slave General Call Address Match Interrupt. [2:2] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADDR_MATCH Slave Address Match Interrupt. [3:3] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 RX_THD Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. [4:4] inactive No interrupt is pending. 0 pending An interrupt is pending. RX_FIFO equal or more bytes than the threshold. 1 TX_THD Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. [5:5] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 STOP STOP Interrupt. [6:6] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 ADDR_ACK Address Acknowledge Interrupt. [7:7] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ARB_ERR Arbritation error Interrupt. [8:8] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TO_ERR timeout Error Interrupt. [9:9] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADDR_NACK_ERR Address NACK Error Interrupt. [10:10] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DATA_ERR Data NACK Error Interrupt. [11:11] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DNR_ERR Do Not Respond Error Interrupt. [12:12] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 START_ERR Start Error Interrupt. [13:13] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 STOP_ERR Stop Error Interrupt. [14:14] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TX_LOCKOUT Transmit Lock Out Interrupt. [15:15] MAMI Multiple Address Match Interrupt [21:16] RD_ADDR_MATCH Slave Read Address Match Interrupt [22:22] WR_ADDR_MATCH Slave Write Address Match Interrupt [23:23] INTEN0 Interrupt Enable Register. 0x0C read-write DONE Transfer Done Interrupt Enable. [0:0] read-write dis Interrupt disabled. 0 en Interrupt enabled when DONE = 1. 1 IRXM Description not available. [1:1] read-write dis Interrupt disabled. 0 en Interrupt enabled when RX_MODE = 1. 1 GC_ADDR_MATCH Slave mode general call address match received input enable. [2:2] read-write dis Interrupt disabled. 0 en Interrupt enabled when GEN_CTRL_ADDR = 1. 1 ADDR_MATCH Slave mode incoming address match interrupt. [3:3] read-write dis Interrupt disabled. 0 en Interrupt enabled when ADDR_MATCH = 1. 1 RX_THD RX FIFO Above Treshold Level Interrupt Enable. [4:4] read-write dis Interrupt disabled. 0 en Interrupt enabled. 1 TX_THD TX FIFO Below Treshold Level Interrupt Enable. [5:5] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOP Stop Interrupt Enable [6:6] read-write dis Interrupt disabled. 0 en Interrupt enabled when STOP = 1. 1 ADDR_ACK Received Address ACK from Slave Interrupt. [7:7] dis Interrupt disabled. 0 en Interrupt enabled. 1 ARB_ERR Master Mode Arbitration Lost Interrupt. [8:8] dis Interrupt disabled. 0 en Interrupt enabled. 1 TO_ERR Timeout Error Interrupt Enable. [9:9] dis Interrupt disabled. 0 en Interrupt enabled. 1 ADDR_NACK_ERR Master Mode Address NACK Received Interrupt. [10:10] dis Interrupt disabled. 0 en Interrupt enabled. 1 DATA_ERR Master Mode Data NACK Received Interrupt. [11:11] dis Interrupt disabled. 0 en Interrupt enabled. 1 DNR_ERR Slave Mode Do Not Respond Interrupt. [12:12] dis Interrupt disabled. 0 en Interrupt enabled. 1 START_ERR Out of Sequence START condition detected interrupt. [13:13] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOP_ERR Out of Sequence STOP condition detected interrupt. [14:14] dis Interrupt disabled. 0 en Interrupt enabled. 1 TX_LOCKOUT TX FIFO Locked Out Interrupt. [15:15] MAMI Multiple Address Match Interrupt [21:16] RD_ADDR_MATCH Slave Read Address Match Interrupt [22:22] WR_ADDR_MATCH Slave Write Address Match Interrupt [23:23] INTFL1 Interrupt Status Register 1. 0x10 RX_OV Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. [0:0] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TX_UN Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 START START Condition Status Flag. [2:2] INTEN1 Interrupt Staus Register 1. 0x14 read-write RX_OV Receiver Overflow Interrupt Enable. [0:0] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 TX_UN Transmit Underflow Interrupt Enable. [1:1] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 START START Condition Interrupt Enable. [2:2] FIFOLEN FIFO Configuration Register. 0x18 RX_DEPTH Receive FIFO Length. [7:0] read-only TX_DEPTH Transmit FIFO Length. [15:8] read-only RXCTRL0 Receive Control Register 0. 0x1C DNR Do Not Respond. [0:0] respond Always respond to address match. 0 not_respond_rx_fifo_empty Do not respond to address match when RX_FIFO is not empty. 1 FLUSH Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. [7:7] not_flushed FIFO not flushed. 0 flush Flush RX_FIFO. 1 THD_LVL Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. [11:8] RXCTRL1 Receive Control Register 1. 0x20 CNT Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. [7:0] LVL Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. [11:8] read-only TXCTRL0 Transmit Control Register 0. 0x24 PRELOAD_MODE Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. [0:0] TX_READY_MODE Transmit FIFO Ready Manual Mode. [1:1] en HW control of I2CTXRDY enabled. 0 dis HW control of I2CTXRDY disabled. 1 GC_ADDR_FLUSH_DIS TX FIFO General Call Address Match Auto Flush Disable. [2:2] en Enabled. 0 dis Disabled. 1 WR_ADDR_FLUSH_DIS TX FIFO Slave Address Match Write Auto Flush Disable. [3:3] en Enabled. 0 dis Disabled. 1 RD_ADDR_FLUSH_DIS TX FIFO Slave Address Match Read Auto Flush Disable. [4:4] en Enabled. 0 dis Disabled. 1 NACK_FLUSH_DIS TX FIFO received NACK Auto Flush Disable. [5:5] en Enabled. 0 dis Disabled. 1 FLUSH Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. [7:7] not_flushed FIFO not flushed. 0 flush Flush TX_FIFO. 1 THD_VAL Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. [11:8] TXCTRL1 Transmit Control Register 1. 0x28 PRELOAD_RDY Transmit FIFO Preload Ready. [0:0] LVL Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. [11:8] read-only FIFO Data Register. 0x2C DATA Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. 0 8 MSTCTRL Master Control Register. 0x30 START Setting this bit to 1 will start a master transfer. [0:0] RESTART Setting this bit to 1 will generate a repeated START. [1:1] STOP Setting this bit to 1 will generate a STOP condition. [2:2] EX_ADDR_EN Slave Extend Address Select. [7:7] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 CLKLO Clock Low Register. 0x34 LO Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. [8:0] CLKHI Clock high Register. 0x38 HI Clock High. In master mode, these bits define the SCL high period. [8:0] HSCLK Clock high Register. 0x3C LO Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. [7:0] HI Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA [15:8] TIMEOUT Timeout Register 0x40 SCL_TO_VAL Timeout [15:0] DMA DMA Register. 0x48 TX_EN TX channel enable. [0:0] dis Disable. 0 en Enable. 1 RX_EN RX channel enable. [1:1] dis Disable. 0 en Enable. 1 4 4 SLAVE_MULTI[%s] Slave Address Register. SLAVE0 0x4C 32 read-write ADDR Slave Address. [9:0] DIS Slave Disable. [10:10] EXT_ADDR_EN Extended Address Select. [15:15] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 SLAVE0 Slave Address Register. 0x4C SLAVE1 Slave Address Register. 0x50 SLAVE2 Slave Address Register. 0x54 SLAVE3 Slave Address Register. 0x58 I2C1 Inter-Integrated Circuit. 1 0x4001E000 I2C1 I2C1 IRQ 36 I2C2 Inter-Integrated Circuit. 2 0x4001F000 I2C2 I2C2 IRQ 62 I2S Inter-IC Sound Interface. I2S 0x40060000 32 0x00 0x1000 registers I2S I2S IRQ 99 CTRL0CH0 Global mode channel. 0x00 LSB_FIRST LSB Transmit Receive First. [1:1] read-write PDM_FILT PDM Filter. [2:2] read-write PDM_EN PDM Enable. [3:3] read-write USEDDR DDR. [4:4] read-write PDM_INV Invert PDM. [5:5] read-write CH_MODE SCK Select. [7:6] read-write WS_POL WS polarity select. [8:8] read-write MSB_LOC MSB location. [9:9] read-only ALIGN Align to MSB or LSB. [10:10] read-only EXT_SEL External SCK/WS selection. [11:11] read-write STEREO Stereo mode of I2S. [13:12] read-only WSIZE Data size when write to FIFO. [15:14] read-write TX_EN TX channel enable. [16:16] read-write RX_EN RX channel enable. [17:17] read-write FLUSH Flushes the TX/RX FIFO buffer. [18:18] read-write RST Write 1 to reset channel. [19:19] read-write FIFO_LSB Bit Field Control. [20:20] read-write RX_THD_VAL depth of receive FIFO for threshold interrupt generation. [31:24] read-write CTRL1CH0 Local channel Setup. 0x10 BITS_WORD I2S word length. [4:0] read-write EN I2S clock enable. [8:8] read-write SMP_SIZE I2S sample size length. [13:9] read-write ADJUST LSB/MSB Justify. [15:15] read-write CLKDIV I2S clock frequency divisor. [31:16] read-write FILTCH0 Filter. 0x20 DMACH0 DMA Control. 0x30 DMA_TX_THD_VAL TX FIFO Level DMA Trigger. [6:0] read-write DMA_TX_EN TX DMA channel enable. [7:7] read-write DMA_RX_THD_VAL RX FIFO Level DMA Trigger. [14:8] read-write DMA_RX_EN RX DMA channel enable. [15:15] read-write TX_LVL Number of data word in the TX FIFO. [23:16] read-write RX_LVL Number of data word in the RX FIFO. [31:24] read-write FIFOCH0 I2S Fifo. 0x40 DATA Load/unload location for TX and RX FIFO buffers. [31:0] read-write INTFL ISR Status. 0x50 RX_OV_CH0 Status for RX FIFO Overrun interrupt. [0:0] read-write RX_THD_CH0 Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. [1:1] read-write TX_OB_CH0 Status for interrupt when TX FIFO has only one byte remaining. [2:2] read-write TX_HE_CH0 Status for interrupt when TX FIFO is half empty. [3:3] read-write INTEN Interrupt Enable. 0x54 RX_OV_CH0 Enable for RX FIFO Overrun interrupt. [0:0] read-write RX_THD_CH0 Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. [1:1] read-write TX_OB_CH0 Enable for interrupt when TX FIFO has only one byte remaining. [2:2] read-write TX_HE_CH0 Enable for interrupt when TX FIFO is half empty. [3:3] read-write EXTSETUP Ext Control. 0x58 EXT_BITS_WORD Word Length for ch_mode. [4:0] read-write WKEN Wakeup Enable. 0x5C WKFL Wakeup Flags. 0x60 ICC0 Instruction Cache Controller Registers 0x4002A000 0x00 0x800 registers INFO Cache ID Register. 0x0000 read-only RELNUM Release Number. Identifies the RTL release version. 0 6 PARTNUM Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. 6 4 ID Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. 10 6 SZ Memory Configuration Register. 0x0004 read-only 0x00080008 CCH Cache Size. Indicates total size in Kbytes of cache. 0 16 MEM Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. 16 16 CTRL Cache Control and Status Register. 0x0100 EN Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. 0 1 dis Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. 0 en Cache Enabled. 1 RDY Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. 16 1 read-only notReady Not Ready. 0 ready Ready. 1 INVALIDATE Invalidate All Registers. 0x0700 read-write INVALID Invalidate. 0 32 LPCMP Low Power Comparator 0x40088000 0x00 0x400 registers LPCMP Low Power Comparato 103 3 4 CTRL[%s] Comparator Control Register. 0x00 EN Comparator Enable. 0 1 POL Polarity Select 5 1 INT_EN IRQ Enable. 6 1 OUT Raw Compartor Input. 14 1 INT_FL IRQ Flag 15 1 LPGCR Low Power Global Control. 0x40080000 0x00 0x400 registers RST Low Power Reset Register. 0x08 GPIO2 Low Power GPIO 2 Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT1 Low Power Watchdog Timer 1 Reset. 1 1 TMR4 Low Power Timer 4 Reset. 2 1 TMR5 Low Power Timer 5 Reset. 3 1 UART3 Low Power UART 3 Reset. 4 1 LPCOMP Low Power Comparator Reset. 6 1 PCLKDIS Low Power Peripheral Clock Disable Register. 0x0C GPIO2 Low Power GPIO 2 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 WDT1 Low Power Watchdog 1 Clock Disable. 1 1 TMR4 Low Power Timer 4 Clock Disable. 2 1 TMR5 Low Power Timer 5 Clock Disable. 3 1 UART3 Low Power UART 3 Clock Disable. 4 1 LPCOMP Low Power Comparator Clock Disable. 6 1 MCR Misc Control. 0x40006C00 0x00 0x400 registers ECCEN ECC Enable Register 0x00 RAM0 ECC System RAM0 Enable. 0 1 dis disabled. 0 en enabled. 1 IPO_MTRIM IPO Manual Register 0x04 MTRIM Manual Trim Value. 0 8 TRIM_RANGE Trim Range Select. 8 1 OUTEN Output Enable Register 0x08 SQWOUT_EN Square Wave Output Enable. 0 1 PDOWN_OUT_EN Power Down Output Enable. 1 1 CMP_CTRL Comparator Control Register. 0x0C EN Comparator Enable. 0 1 POL Polarity Select 5 1 INT_EN IRQ Enable. 6 1 OUT Comparator Output State. 14 1 INT_FL IRQ Flag 15 1 CTRL Miscellaneous Control Register. 0x10 INRO_EN INRO Enable. 2 1 ERTCO_EN ERTCO Enable. 3 1 SIMO_CLKSCL_EN SIMO Clock Scaling Enable. 8 1 SIMO_RSTD SIMO System Reset Disable. 9 1 GPIO3_CTRL GPIO3 Pin Control Register. 0x20 P30_DO GPIO3 Pin 0 Data Output. 0 1 P30_OE GPIO3 Pin 0 Output Enable. 1 1 P30_PE GPIO3 Pin 0 Pull-up Enable. 2 1 P30_IN GPIO3 Pin 0 Input Status. 3 1 P31_DO GPIO3 Pin 1 Data Output. 4 1 P31_OE GPIO3 Pin 1 Output Enable. 5 1 P31_PE GPIO3 Pin 1 Pull-up Enable. 6 1 P31_IN GPIO3 Pin 1 Input Status. 7 1 OWM 1-Wire Master Interface. 0x4003D000 32 read-write 0 0x1000 registers OneWire 67 CFG 1-Wire Master Configuration. 0x0000 read-write long_line_mode Long Line Mode. [0:0] read-write force_pres_det Force Line During Presence Detect. [1:1] read-write bit_bang_en Bit Bang Enable. [2:2] read-write ext_pullup_mode Provide an extra output control to control an external pullup. [3:3] read-write ext_pullup_enable Enable External Pullup. [4:4] read-write single_bit_mode Enable Single Bit TX/RX Mode. [5:5] read-write overdrive Enables overdrive speed for 1-Wire operations. [6:6] read-write int_pullup_enable Enable intenral pullup. [7:7] read-write CLK_DIV_1US 1-Wire Master Clock Divisor. 0x0004 read-write divisor Clock Divisor for 1Mhz. [7:0] read-write CTRL_STAT 1-Wire Master Control/Status. 0x0008 read-write start_ow_reset Start OW Reset. [0:0] read-write sra_mode SRA Mode. [1:1] read-write bit_bang_oe Bit Bang Output Enable. [2:2] read-write ow_input OW Input State. [3:3] read-only od_spec_mode Overdrive Spec Mode. [4:4] read-only presence_detect Presence Pulse Detected. [7:7] read-only DATA 1-Wire Master Data Buffer. 0x000C read-write tx_rx TX/RX Buffer. [7:0] read-write INTFL 1-Wire Master Interrupt Flags. 0x0010 read-write ow_reset_done OW Reset Sequence Completed. [0:0] read-write tx_data_empty TX Data Empty Interrupt Flag. [1:1] read-write rx_data_ready RX Data Ready Interrupt Flag [2:2] read-write line_short OW Line Short Detected Interrupt Flag. [3:3] read-write line_low OW Line Low Detected Interrupt Flag. [4:4] read-write INTEN 1-Wire Master Interrupt Enables. 0x0014 read-write ow_reset_done OW Reset Sequence Completed. [0:0] read-write oneToClear tx_data_empty Tx Data Empty Interrupt Enable. [1:1] read-write oneToClear rx_data_ready Rx Data Ready Interrupt Enable. [2:2] read-write oneToClear line_short OW Line Short Detected Interrupt Enable. [3:3] read-write oneToClear line_low OW Line Low Detected Interrupt Enable. [4:4] read-write oneToClear PT Pulse Train Pulse_Train 0x4003C020 32 read-write 0 0x0010 registers RATE_LENGTH Pulse Train Configuration 0x0000 read-write rate_control Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train. 0 27 read-write mode Pulse Train Output Mode/Train Length 27 5 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 2_BIT Pulse train, 2 bit pattern. 2 3_BIT Pulse train, 3 bit pattern. 3 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 TRAIN Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length. 0x0004 read-write LOOP Pulse Train Loop Count 0x0008 read-write count Number of loops for this pulse train to repeat. 0 16 read-write delay Delay between loops of the Pulse Train in PT Peripheral Clock cycles 16 12 read-write RESTART Pulse Train Auto-Restart Configuration. 0x000C read-write pt_x_select Auto-Restart PT X Select 0 5 read-write on_pt_x_loop_exit Enable Auto-Restart on PT X Loop Exit 7 1 read-write pt_y_select Auto-Restart PT Y Select 8 5 read-write on_pt_y_loop_exit Enable Auto-Restart on PT Y Loop Exit 15 1 read-write PT1 Pulse Train 1 0x4003C030 PT2 Pulse Train 2 0x4003C040 PT3 Pulse Train 3 0x4003C050 PTG Pulse Train Generation Pulse_Train 0x4003C000 32 read-write 0 0x0020 registers PT Pulse Train IRQ 59 ENABLE Global Enable/Disable Controls for All Pulse Trains 0x0000 read-write pt0 Enable/Disable control for PT0 0 1 read-write pt1 Enable/Disable control for PT1 1 1 read-write pt2 Enable/Disable control for PT2 2 1 read-write pt3 Enable/Disable control for PT3 3 1 read-write RESYNC Global Resync (All Pulse Trains) Control 0x0004 read-write pt0 Resync control for PT0 0 1 read-write pt1 Resync control for PT1 1 1 read-write pt2 Resync control for PT2 2 1 read-write pt3 Resync control for PT3 3 1 read-write INTFL Pulse Train Interrupt Flags 0x0008 read-write pt0 Pulse Train 0 Stopped Interrupt Flag 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Flag 1 1 read-write pt2 Pulse Train 2 Stopped Interrupt Flag 2 1 read-write pt3 Pulse Train 3 Stopped Interrupt Flag 3 1 read-write INTEN Pulse Train Interrupt Enable/Disable 0x000C read-write pt0 Pulse Train 0 Stopped Interrupt Enable/Disable 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Enable/Disable 1 1 read-write pt2 Pulse Train 2 Stopped Interrupt Enable/Disable 2 1 read-write pt3 Pulse Train 3 Stopped Interrupt Enable/Disable 3 1 read-write SAFE_EN Pulse Train Global Safe Enable. 0x0010 write-only PT0 0 1 write-only PT1 1 1 write-only PT2 2 1 write-only PT3 3 1 write-only SAFE_DIS Pulse Train Global Safe Disable. 0x0014 write-only PT0 0 1 write-only PT1 1 1 write-only PT2 2 1 write-only PT3 3 1 write-only PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers LPCN Low Power Control Register. 0x00 RAMRET0 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 1 dis Disable Ram Retention. 0 en Enable System RAM 0 retention. 1 RAMRET1 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 1 1 dis Disable Ram Retention. 0 en Enable System RAM 1 retention. 1 RAMRET2 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 2 1 dis Disable Ram Retention. 0 en Enable System RAM 2 retention. 1 RAMRET3 System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 3 1 dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 LPMCLKSEL Low Power Mode APB Clock Select. 8 1 LPMFAST Low Power Mode Clock Select. 9 1 BG_DIS Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode (default). 1 LPWKST_CLR Low Power Wakeup Status Register Clear 31 1 LPWKST0 Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 1 LPWKEN0 Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 LPWKST1 Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C LPWKEN1 Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 LPWKST2 Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2. 0x14 LPWKEN2 Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2. 0x18 LPWKST3 Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3. 0x1C LPWKEN3 Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3. 0x20 LPPWST Low Power Peripheral Wakeup Status Register. 0x30 AINCOMP0 Analog Input Comparator Wakeup Flag. 4 1 BACKUP Backup Mode Wakeup Flag. 16 1 RESET Reset Detected Wakeup Flag. 17 1 LPPWEN Low Power Peripheral Wakeup Enable Register. 0x34 AINCOMP0 AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. 4 1 WDT0 WDT0 Wakeup Enable. This bit allows wakeup from the WDT0. 8 1 WDT1 WDT1 Wakeup Enable. This bit allows wakeup from the WDT1. 9 1 CPU1 CPU1 Wakeup Enable. This bit allows wakeup from the CPU1. 10 1 TMR0 TMR0 Wakeup Enable. This bit allows wakeup from the TMR0. 11 1 TMR1 TMR1 Wakeup Enable. This bit allows wakeup from the TMR1. 12 1 TMR2 TMR2 Wakeup Enable. This bit allows wakeup from the TMR2. 13 1 TMR3 TMR3 Wakeup Enable. This bit allows wakeup from the TMR3. 14 1 TMR4 TMR4 Wakeup Enable. This bit allows wakeup from the TMR4. 15 1 TMR5 TMR5 Wakeup Enable. This bit allows wakeup from the TMR5. 16 1 UART0 UART0 Wakeup Enable. This bit allows wakeup from the UART0. 17 1 UART1 UART1 Wakeup Enable. This bit allows wakeup from the UART1. 18 1 UART2 UART2 Wakeup Enable. This bit allows wakeup from the UART2. 19 1 UART3 UART3 Wakeup Enable. This bit allows wakeup from the UART3. 20 1 I2C0 I2C0 Wakeup Enable. This bit allows wakeup from the I2C0. 21 1 I2C1 I2C1 Wakeup Enable. This bit allows wakeup from the I2C1. 22 1 I2C2 I2C2 Wakeup Enable. This bit allows wakeup from the I2C2. 23 1 I2S I2S Wakeup Enable. This bit allows wakeup from the I2S. 24 1 SPI1 SPI1 Wakeup Enable. This bit allows wakeup from the SPI1. 25 1 LPCMP LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP. 26 1 GP0 General Purpose Register 0 0x48 GP1 General Purpose Register 1 0x4C RTC Real Time Clock and Alarm. 0x40006000 0x00 0x400 registers RTC RTC interrupt. 3 SEC RTC Second Counter. This register contains the 32-bit second counter. 0x00 0x00000000 SEC Seconds Counter. 0 32 SSEC RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 SSEC Sub-Seconds Counter (12-bit). 0 12 TODA Time-of-day Alarm. 0x08 0x00000000 TOD_ALARM Time-of-day Alarm. 0 20 SSECA RTC sub-second alarm. This register contains the reload value for the sub-second alarm. 0x0C 0x00000000 SSEC_ALARM This register contains the reload value for the sub-second alarm. 0 32 CTRL RTC Control Register. 0x10 0x00000008 0xFFFFFF38 EN Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 TOD_ALARM_IE Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 SSEC_ALARM_IE Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 RDY RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 4 1 busy Register has not updated. 0 ready Ready. 1 RDY_IE RTC Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 TOD_ALARM Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active 0 Pending Active 1 SSEC_ALARM Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active 0 Pending Active 1 SQW_EN Square Wave Output Enable. 8 1 inactive Not active 0 Pending Active 1 SQW_SEL Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 9 2 freq1Hz 1 Hz (Compensated). 0 freq512Hz 512 Hz (Compensated). 1 freq4KHz 4 KHz. 2 clkDiv8 RTC Input Clock / 8. 3 RD_EN Asynchronous Counter Read Enable. 14 1 WR_EN Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 15 1 inactive Not active 0 Pending Active 1 TRIM RTC Trim Register. 0x14 0x00000000 TRIM RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. 0 8 VRTC_TMR VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. 8 24 OSCCTRL RTC Oscillator Control Register. 0x18 0x00000000 FILTER_EN Enables analog deglitch filter. 0 1 IBIAS_SEL If IBIAS_EN is 1, selects 4x,2x mode. 1 1 HYST_EN Enables high current hysteresis buffer. 2 1 IBIAS_EN Enables higher 4x,2x current modes. 3 1 BYPASS RTC Crystal Bypass 4 1 SQW_32K RTC 32kHz Square Wave Output 5 1 SEMA The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. 0x4003E000 0x00 0x1000 registers 8 4 SEMAPHORES[%s] Read to test and set, returns prior value. Write 0 to clear semaphore. 0x00 32 sema 0 1 irq0 Semaphore IRQ0 register. 0x40 32 en 0 1 cm4_irq 16 1 mail0 Semaphore Mailbox 0 register. 0x44 32 data 0 32 irq1 Semaphore IRQ1 register. 0x48 32 en 0 1 rv32_irq 16 1 mail1 Semaphore Mailbox 1 register. 0x4C 32 data 0 32 status Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. 0x100 32 status0 0 1 status1 1 1 status2 2 1 status3 3 1 status4 4 1 status5 5 1 status6 6 1 status7 7 1 SIMO Single Inductor Multiple Output Switching Converter 0x40004400 0x00 0x400 registers VREGO_A Buck Voltage Regulator A Control Register 0x0004 read-write VSETA Regulator Output Voltage Setting 0 7 RANGEA Regulator Output Range Set 7 1 low Low output voltage range 0 high High output voltage range 1 VREGO_B Buck Voltage Regulator B Control Register 0x0008 read-write VSETB Regulator Output Voltage Setting 0 7 RANGEB Regulator Output Range Set 7 1 low Low output voltage range 0 high High output voltage range 1 VREGO_C Buck Voltage Regulator C Control Register 0x000C read-write VSETC Regulator Output Voltage Setting 0 7 RANGEC Regulator Output Range Set 7 1 low Low output voltage range 0 high High output voltage range 1 VREGO_D Buck Voltage Regulator D Control Register 0x0010 read-write VSETD Regulator Output Voltage Setting 0 7 RANGED Regulator Output Range Set 7 1 low Low output voltage range 0 high High output voltage range 1 IPKA High Side FET Peak Current VREGO_A/VREGO_B Register 0x0014 read-write IPKSETA Voltage Regulator Peak Current Setting 0 4 IPKSETB Voltage Regulator Peak Current Setting 4 4 IPKB High Side FET Peak Current VREGO_C/VREGO_D Register 0x0018 read-write IPKSETC Voltage Regulator Peak Current Setting 0 4 IPKSETD Voltage Regulator Peak Current Setting 4 4 MAXTON Maximum High Side FET Time On Register 0x001C read-write TONSET Sets the maximum on time for the high side FET, each increment represents 500ns 0 4 ILOAD_A Buck Cycle Count VREGO_A Register 0x0020 read-only ILOADA Number of buck cycles that occur within the cycle clock 0 8 ILOAD_B Buck Cycle Count VREGO_B Register 0x0024 read-only ILOADB Number of buck cycles that occur within the cycle clock 0 8 ILOAD_C Buck Cycle Count VREGO_C Register 0x0028 read-only ILOADC Number of buck cycles that occur within the cycle clock 0 8 ILOAD_D Buck Cycle Count VREGO_D Register 0x002C read-only ILOADD Number of buck cycles that occur within the cycle clock 0 8 BUCK_ALERT_THR_A Buck Cycle Count Alert VERGO_A Register 0x0030 read-write BUCKTHRA Threshold for ILOADA to generate the BUCK_ALERT 0 8 BUCK_ALERT_THR_B Buck Cycle Count Alert VERGO_B Register 0x0034 read-write BUCKTHRB Threshold for ILOADB to generate the BUCK_ALERT 0 8 BUCK_ALERT_THR_C Buck Cycle Count Alert VERGO_C Register 0x0038 read-write BUCKTHRC Threshold for ILOADC to generate the BUCK_ALERT 0 8 BUCK_ALERT_THR_D Buck Cycle Count Alert VERGO_D Register 0x003C read-write BUCKTHRD Threshold for ILOADD to generate the BUCK_ALERT 0 8 BUCK_OUT_READY Buck Regulator Output Ready Register 0x0040 read-only BUCKOUTRDYA When set, indicates that the output voltage has reached its regulated value 0 1 notrdy Output voltage not in range 0 rdy Output voltage in range 1 BUCKOUTRDYB When set, indicates that the output voltage has reached its regulated value 1 1 BUCKOUTRDYC When set, indicates that the output voltage has reached its regulated value 2 1 BUCKOUTRDYD When set, indicates that the output voltage has reached its regulated value 3 1 ZERO_CROSS_CAL_A Zero Cross Calibration VERGO_A Register 0x0044 read-only ZXCALA Zero Cross Calibrartion Value VREGO_A 0 4 ZERO_CROSS_CAL_B Zero Cross Calibration VERGO_B Register 0x0048 read-only ZXCALB Zero Cross Calibrartion Value VREGO_B 0 4 ZERO_CROSS_CAL_C Zero Cross Calibration VERGO_C Register 0x004C read-only ZXCALC Zero Cross Calibrartion Value VREGO_C 0 4 ZERO_CROSS_CAL_D Zero Cross Calibration VERGO_D Register 0x0050 read-only ZXCALD Zero Cross Calibrartion Value VREGO_D 0 4 SIR System Initialization Registers. 0x40000400 read-only 0x00 0x400 registers SISTAT System Initialization Status Register. 0x00 read-only MAGIC Magic Word Validation. This bit is set by the system initialization block following power-up. 0 1 read-only read magicNotSet Magic word was not set (OTP has not been initialized properly). 0 magicSet Magic word was set (OTP contains valid settings). 1 CRCERR CRC Error Status. This bit is set by the system initialization block following power-up. 1 1 read-only read noError No CRC errors occurred during the read of the OTP memory block. 0 error A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. 1 ADDR Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x04 read-only ERRADDR 0 32 FSTAT funcstat register. 0x100 read-only FPU FPU Function. 0 1 no 0 yes 1 ADC 10-bit Sigma Delta ADC. 2 1 no 0 yes 1 SMPHR SMPHR function. 7 1 no 0 yes 1 SFSTAT Security function status register. 0x104 read-only TRNG TRNG Function. 0 1 no 0 yes 1 AES AES Block. 2 1 no 0 yes 1 SPI0 SPI peripheral. 0x400BE000 0x00 0x1000 registers SPI0 56 FIFO32 Register for reading and writing the FIFO. 0x00 32 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 32 2 2 FIFO16[%s] Register for reading and writing the FIFO. 0x00 16 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 16 4 1 FIFO8[%s] Register for reading and writing the FIFO. 0x00 8 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 8 CTRL0 Register for controlling SPI peripheral. 0x04 read-write EN SPI Enable. 0 1 dis SPI is disabled. 0 en SPI is enabled. 1 MST_MODE Master Mode Enable. 1 1 dis SPI is Slave mode. 0 en SPI is Master mode. 1 SS_IO Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 4 1 output Slave select 0 is output. 0 input Slave Select 0 is input, only valid if MMEN=1. 1 START Start Transmit. 5 1 start Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. 1 SS_CTRL Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. 8 1 DEASSERT SPI De-asserts Slave Select at the end of a transaction. 0 ASSERT SPI leaves Slave Select asserted at the end of a transaction. 1 SS_ACTIVE Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 16 4 SS0 SS0 is selected. 0x1 SS1 SS1 is selected. 0x2 SS2 SS2 is selected. 0x4 SS3 SS3 is selected. 0x8 CTRL1 Register for controlling SPI peripheral. 0x08 read-write TX_NUM_CHAR Nubmer of Characters to transmit. 0 16 RX_NUM_CHAR Nubmer of Characters to receive. 16 16 CTRL2 Register for controlling SPI peripheral. 0x0C read-write CLKPHA Clock Phase. 0 1 Rising_Edge Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 0 Falling_Edge Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 1 CLKPOL Clock Polarity. 1 1 Normal Normal Clock. Use when in SPI Mode 0 and Mode 1 0 Inverted Inverted Clock. Use when in SPI Mode 2 and Mode 3 1 NUMBITS Number of Bits per character. 8 4 16 16 bits per character. 0 1 1 bits per character. 1 2 2 bits per character. 2 3 3 bits per character. 3 4 4 bits per character. 4 5 5 bits per character. 5 6 6 bits per character. 6 7 7 bits per character. 7 8 8 bits per character. 8 9 9 bits per character. 9 10 10 bits per character. 10 11 11 bits per character. 11 12 12 bits per character. 12 13 13 bits per character. 13 14 14 bits per character. 14 15 15 bits per character. 15 DATA_WIDTH SPI Data width. 12 2 Mono 1 data pin. 0 Dual 2 data pins. 1 Quad 4 data pins. 2 THREE_WIRE Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 15 1 dis Use four wire mode (Mono only). 0 en Use three wire mode. 1 SS_POL Slave Select Polarity, each Slave Select can have unique polarity. 16 8 SS0_high SS0 active high. 0x1 SS1_high SS1 active high. 0x2 SS2_high SS2 active high. 0x4 SS3_high SS3 active high. 0x8 SSTIME Register for controlling SPI peripheral/Slave Select Timing. 0x10 read-write PRE Slave Select Pre delay 1. 0 8 256 256 system clocks between SS active and first serial clock edge. 0 POST Slave Select Post delay 2. 8 8 256 256 system clocks between last serial clock edge and SS inactive. 0 INACT Slave Select Inactive delay. 16 8 256 256 system clocks between transactions. 0 CLKCTRL Register for controlling SPI clock rate. 0x14 read-write LO Low duty cycle control. In timer mode, reload[7:0]. 0 8 Dis Duty cycle control of serial clock generation is disabled. 0 HI High duty cycle control. In timer mode, reload[15:8]. 8 8 Dis Duty cycle control of serial clock generation is disabled. 0 CLKDIV System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. 16 4 DMA Register for controlling DMA. 0x1C read-write TX_THD_VAL Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. 0 5 TX_FIFO_EN Transmit FIFO enabled for SPI transactions. 6 1 dis Transmit FIFO is not enabled. 0 en Transmit FIFO is enabled. 1 TX_FLUSH Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 7 1 CLEAR Clear the Transmit FIFO, clears any pending TX FIFO status. 1 TX_LVL Count of entries in TX FIFO. 8 6 read-only DMA_TX_EN TX DMA Enable. 15 1 DIS TX DMA requests are disabled, andy pending DMA requests are cleared. 0 en TX DMA requests are enabled. 1 RX_THD_VAL Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. 16 5 RX_FIFO_EN Receive FIFO enabled for SPI transactions. 22 1 DIS Receive FIFO is not enabled. 0 en Receive FIFO is enabled. 1 RX_FLUSH Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 23 1 CLEAR Clear the Receive FIFO, clears any pending RX FIFO status. 1 RX_LVL Count of entries in RX FIFO. 24 6 read-only DMA_RX_EN RX DMA Enable. 31 1 dis RX DMA requests are disabled, any pending DMA requests are cleared. 0 en RX DMA requests are enabled. 1 INTFL Register for reading and clearing interrupt flags. All bits are write 1 to clear. 0x20 read-write TX_THD TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL RX FIFO FULL. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSA Slave Select Asserted. 4 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSD Slave Select Deasserted. 5 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 FAULT Multi-Master Mode Fault. 8 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 ABORT Slave Abort Detected. 9 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 MST_DONE Master Done, set when SPI Master has completed any transactions. 11 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_OV Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 12 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_UN Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. 13 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_OV Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. 14 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_UN Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. 15 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 INTEN Register for enabling interrupts. 0x24 read-write TX_THD TX FIFO Threshold interrupt enable. 0 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_EM TX FIFO Empty interrupt enable. 1 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_THD RX FIFO Threshold Crossed interrupt enable. 2 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_FULL RX FIFO FULL interrupt enable. 3 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSA Slave Select Asserted interrupt enable. 4 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSD Slave Select Deasserted interrupt enable. 5 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 FAULT Multi-Master Mode Fault interrupt enable. 8 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 ABORT Slave Abort Detected interrupt enable. 9 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 MST_DONE Master Done interrupt enable. 11 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_OV Transmit FIFO Overrun interrupt enable. 12 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_UN Transmit FIFO Underrun interrupt enable. 13 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_OV Receive FIFO Overrun interrupt enable. 14 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_UN Receive FIFO Underrun interrupt enable. 15 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 WKFL Register for wake up flags. All bits in this register are write 1 to clear. 0x28 read-write TX_THD Wake on TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM Wake on TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD Wake on RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL Wake on RX FIFO Full. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 WKEN Register for wake up enable. 0x2C read-write TX_THD Wake on TX FIFO Threshold Crossed Enable. 0 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 TX_EM Wake on TX FIFO Empty Enable. 1 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_THD Wake on RX FIFO Threshold Crossed Enable. 2 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_FULL Wake on RX FIFO Full Enable. 3 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 STAT SPI Status register. 0x30 read-only BUSY SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 0 1 not SPI not active. 0 active SPI active. 1 SPI1 SPI peripheral. 1 0x40046000 SPI1 SPI1 IRQ 32 TMR Low-Power Configurable Timer 0x40010000 0x00 0x1000 registers TMR 5 CNT Timer Counter Register. 0x00 read-write COUNT The current count value for the timer. This field increments as the timer counts. 0 32 CMP Timer Compare Register. 0x04 read-write COMPARE The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. 0 32 PWM Timer PWM Register. 0x08 read-write PWM Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. 0 32 INTFL Timer Interrupt Status Register. 0x0C read-write IRQ_A Interrupt Flag for Timer A. 0 1 WRDONE_A Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. 8 1 WR_DIS_A Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. 9 1 IRQ_B Interrupt Flag for Timer B. 16 1 WRDONE_B Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. 24 1 WR_DIS_B Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. 25 1 CTRL0 Timer Control Register. 0x10 read-write MODE_A Mode Select for Timer A 0 4 ONE_SHOT One-Shot Mode 0 CONTINUOUS Continuous Mode 1 COUNTER Counter Mode 2 PWM PWM Mode 3 CAPTURE Capture Mode 4 COMPARE Compare Mode 5 GATED Gated Mode 6 CAPCOMP Capture/Compare Mode 7 DUAL_EDGE Dual Edge Capture Mode 8 IGATED Inactive Gated Mode 14 CLKDIV_A Clock Divider Select for Timer A 4 4 DIV_BY_1 Prescaler Divide-By-1 0 DIV_BY_2 Prescaler Divide-By-2 1 DIV_BY_4 Prescaler Divide-By-4 2 DIV_BY_8 Prescaler Divide-By-8 3 DIV_BY_16 Prescaler Divide-By-16 4 DIV_BY_32 Prescaler Divide-By-32 5 DIV_BY_64 Prescaler Divide-By-64 6 DIV_BY_128 Prescaler Divide-By-128 7 DIV_BY_256 Prescaler Divide-By-256 8 DIV_BY_512 Prescaler Divide-By-512 9 DIV_BY_1024 Prescaler Divide-By-1024 10 DIV_BY_2048 Prescaler Divide-By-2048 11 DIV_BY_4096 TBD 12 POL_A Timer Polarity for Timer A 8 1 PWMSYNC_A PWM Synchronization Mode for Timer A 9 1 NOLHPOL_A PWM Phase A (Non-Overlapping High) Polarity for Timer A 10 1 NOLLPOL_A PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A 11 1 PWMCKBD_A PWM Phase A-Prime Output Disable for Timer A 12 1 RST_A Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. 13 1 CLKEN_A Write 1 to Enable CLK_TMR for Timer A 14 1 EN_A Enable for Timer A 15 1 MODE_B Mode Select for Timer B 16 4 ONE_SHOT One-Shot Mode 0 CONTINUOUS Continuous Mode 1 COUNTER Counter Mode 2 PWM PWM Mode 3 CAPTURE Capture Mode 4 COMPARE Compare Mode 5 GATED Gated Mode 6 CAPCOMP Capture/Compare Mode 7 DUAL_EDGE Dual Edge Capture Mode 8 IGATED Inactive Gated Mode 14 CLKDIV_B Clock Divider Select for Timer B 20 4 DIV_BY_1 Prescaler Divide-By-1 0 DIV_BY_2 Prescaler Divide-By-2 1 DIV_BY_4 Prescaler Divide-By-4 2 DIV_BY_8 Prescaler Divide-By-8 3 DIV_BY_16 Prescaler Divide-By-16 4 DIV_BY_32 Prescaler Divide-By-32 5 DIV_BY_64 Prescaler Divide-By-64 6 DIV_BY_128 Prescaler Divide-By-128 7 DIV_BY_256 Prescaler Divide-By-256 8 DIV_BY_512 Prescaler Divide-By-512 9 DIV_BY_1024 Prescaler Divide-By-1024 10 DIV_BY_2048 Prescaler Divide-By-2048 11 DIV_BY_4096 TBD 12 POL_B Timer Polarity for Timer B 24 1 PWMSYNC_B PWM Synchronization Mode for Timer B 25 1 NOLHPOL_B PWM Phase A (Non-Overlapping High) Polarity for Timer B 26 1 NOLLPOL_B PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B 27 1 PWMCKBD_B PWM Phase A-Prime Output Disable for Timer B 28 1 RST_B Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. 29 1 CLKEN_B Write 1 to Enable CLK_TMR for Timer B 30 1 EN_B Enable for Timer B 31 1 NOLCMP Timer Non-Overlapping Compare Register. 0x14 read-write LO_A Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. 0 8 HI_A Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. 8 8 LO_B Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. 16 8 HI_B Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. 24 8 CTRL1 Timer Configuration Register. 0x18 read-write CLKSEL_A Timer Clock Select for Timer A 0 2 CLKEN_A Timer A Enable Status 2 1 CLKRDY_A CLK_TMR Ready Flag for Timer A 3 1 EVENT_SEL_A Event Select for Timer A 4 3 NEGTRIG_A Negative Edge Trigger for Event for Timer A 7 1 IE_A Interrupt Enable for Timer A 8 1 CAPEVENT_SEL_A Capture Event Select for Timer A 9 2 SW_CAPEVENT_A Software Capture Event for Timer A 11 1 WE_A Wake-Up Enable for Timer A 12 1 OUTEN_A OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A 13 1 OUTBEN_A PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A 14 1 CLKSEL_B Timer Clock Select for Timer B 16 2 CLKEN_B Timer B Enable Status 18 1 CLKRDY_B CLK_TMR Ready Flag for Timer B 19 1 EVENT_SEL_B Event Select for Timer B 20 3 NEGTRIG_B Negative Edge Trigger for Event for Timer B 23 1 IE_B Interrupt Enable for Timer B 24 1 CAPEVENT_SEL_B Capture Event Select for Timer B 25 2 SW_CAPEVENT_B Software Capture Event for Timer B 27 1 WE_B Wake-Up Enable for Timer B 28 1 CASCADE Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. 31 1 WKFL Timer Wakeup Status Register. 0x1C read-write A Wake-Up Flag for Timer A 0 1 B Wake-Up Flag for Timer B 16 1 TMR1 Low-Power Configurable Timer 1 0x40011000 TMR1 TMR1 IRQ 6 TMR2 Low-Power Configurable Timer 2 0x40012000 TMR2 TMR2 IRQ 7 TMR3 Low-Power Configurable Timer 3 0x40013000 TMR3 TMR3 IRQ 8 TMR4 Low-Power Configurable Timer 4 0x40080C00 TMR4 TMR4 IRQ 9 TMR5 Low-Power Configurable Timer 5 0x40081000 TMR5 TMR5 IRQ 10 TRIMSIR Trim System Initilazation Registers 0x40005400 0x00 0x400 registers RTC RTC Trim System Initialization Register. 0x08 X1TRIM RTC X1 Trim. 16 5 X2TRIM RTC X2 Trim. 21 5 LOCK Lock. 31 1 SIMO SIMO Trim System Initialization Register. 0x34 read-only CLKDIV SIMO Clock Divide. 0 3 DIV1 0 DIV16 1 DIV32 3 DIV64 5 DIV128 7 IPOLO IPO Low Trim System Initialization Register. 0x3C read-only IPO_LIMITLO IPO Low Limit Trim. 0 8 CTRL Control Trim System Initialization Register. 0x40 VDDA_LIMITLO VDDA Low Trim Limit. 0 7 VDDA_LIMITHI VDDA High Trim Limit. 8 7 IPO_LIMITHI IPO High Trim Limit. 15 9 INRO_SEL INRO Clock Select. 24 2 8KHZ 0 16KHZ 1 30KHZ 2 INRO_TRIM INRO Clock Trim. 29 3 INRO RTC Trim System Initialization Register. 0x44 TRIM16K INRO 16KHz Trim. 0 3 TRIM30K INRO 30KHz Trim. 3 3 LPCLKSEL INRO Low Power Mode Clock Select. 6 2 8KHZ 0 16KHZ 1 30KHZ 2 TRNG Random Number Generator. 0x4004D000 0x00 0x1000 registers TRNG TRNG interrupt. 4 CTRL TRNG Control Register. 0x00 0x00000003 RND_IE To enable IRQ generation when a new 32-bit Random number is ready. 1 1 disable Disable 0 enable Enable 1 KEYGEN AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. 3 1 KEYWIPE To wipe the Battery Backed key. 15 1 STATUS Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x04 RDY 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. 0 1 Busy TRNG Busy 0 Ready 32 bit random data is ready 1 DATA Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x08 read-only DATA Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. 0 32 UART UART Low Power Registers 0x40042000 0x00 0x1000 registers CTRL Control register 0x0000 RX_THD_VAL This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) 0 4 PAR_EN Parity Enable 4 1 PAR_EO when PAREN=1 selects odd or even parity odd is 1 even is 0 5 1 PAR_MD Selects parity based on 1s or 0s count (when PAREN=1) 6 1 CTS_DIS CTS Sampling Disable 7 1 TX_FLUSH Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. 8 1 RX_FLUSH Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. 9 1 CHAR_SIZE Selects UART character size 10 2 5bits 5 bits 0 6bits 6 bits 1 7bits 7 bits 2 8bits 8 bits 3 STOPBITS Selects the number of stop bits that will be generated 12 1 HFC_EN Enables/disables hardware flow control 13 1 RTSDC Hardware Flow Control RTS Mode 14 1 BCLKEN Baud clock enable 15 1 BCLKSRC To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. 16 2 Peripheral_Clock apb clock 0 External_Clock Clock 1 1 CLK2 Clock 2 2 CLK3 Clock 3 3 DPFE_EN Data/Parity bit frame error detection enable 18 1 BCLKRDY Baud clock Ready read only bit 19 1 UCAGM UART Clock Auto Gating mode 20 1 FDM Fractional Division Mode 21 1 DESM RX Dual Edge Sampling Mode 22 1 STATUS Status register 0x0004 read-only TX_BUSY Read-only flag indicating the UART transmit status 0 1 RX_BUSY Read-only flag indicating the UART receiver status 1 1 RX_EM Read-only flag indicating the RX FIFO state 4 1 RX_FULL Read-only flag indicating the RX FIFO state 5 1 TX_EM Read-only flag indicating the TX FIFO state 6 1 TX_FULL Read-only flag indicating the TX FIFO state 7 1 RX_LVL Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) 8 4 TX_LVL Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) 12 4 INT_EN Interrupt Enable control register 0x0008 RX_FERR Enable Interrupt For RX Frame Error 0 1 RX_PAR Enable Interrupt For RX Parity Error 1 1 CTS_EV Enable Interrupt For CTS signal change Error 2 1 RX_OV Enable Interrupt For RX FIFO Overrun Error 3 1 RX_THD Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD 4 1 TX_OB Enable Interrupt For TX FIFO has one byte remaining 5 1 TX_HE Enable Interrupt For TX FIFO has half empty 6 1 INT_FL Interrupt status flags Control register 0x000C RX_FERR Flag for RX Frame Error Interrupt. 0 1 RX_PAR Flag for RX Parity Error interrupt 1 1 CTS_EV Flag for CTS signal change interrupt (hardware flow control disabled) 2 1 RX_OV Flag for RX FIFO Overrun interrupt 3 1 RX_THD Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field 4 1 TX_OB Flag for interrupt when TX FIFO has one byte remaining 5 1 TX_HE Flag for interrupt when TX FIFO is half empty 6 1 CLKDIV Clock Divider register 0x0010 CLKDIV Baud rate divisor value 0 20 OSR Over Sampling Rate register 0x0014 OSR OSR 0 3 TXPEEK TX FIFO Output Peek register 0x0018 DATA Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field. 0 8 PNR Pin register 0x001C CTS Current sampled value of CTS IO 0 1 read-only RTS This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level. 1 1 FIFO FIFO Read/Write register 0x0020 DATA Load/unload location for TX and RX FIFO buffers. 0 8 RX_PAR Parity error flag for next byte to be read from FIFO. 8 1 DMA DMA Configuration register 0x0030 TX_THD_VAL TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory. 0 4 TX_EN TX DMA channel enable 4 1 RX_THD_VAL Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory. 5 4 RX_EN RX DMA channel enable 9 1 WKEN Wake up enable Control register 0x0034 RX_NE Wake-Up Enable for RX FIFO Not Empty 0 1 RX_FULL Wake-Up Enable for RX FIFO Full 1 1 RX_THD Wake-Up Enable for RX FIFO Threshold Met 2 1 WKFL Wake up Flags register 0x0038 RX_NE Wake-Up Flag for RX FIFO Not Empty 0 1 RX_FULL Wake-Up Flag for RX FIFO Full 1 1 RX_THD Wake-Up Flag for RX FIFO Threshold Met 2 1 UART1 UART Low Power Registers 1 0x40043000 UART2 UART Low Power Registers 2 0x40044000 UART3 UART Low Power Registers 3 0x40081400 WDT Windowed Watchdog Timer 0x40003000 0x00 0x0400 registers WWDT 1 CTRL Watchdog Timer Control Register. 0x00 read-write INT_LATE_VAL Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_LATE_VAL Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 4 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 EN Windowed Watchdog Timer Enable. 8 1 dis Disable. 0 en Enable. 1 INT_LATE Windowed Watchdog Timer Interrupt Flag Too Late. 9 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 WDT_INT_EN Windowed Watchdog Timer Interrupt Enable. 10 1 dis Disable. 0 en Enable. 1 WDT_RST_EN Windowed Watchdog Timer Reset Enable. 11 1 dis Disable. 0 en Enable. 1 INT_EARLY Windowed Watchdog Timer Interrupt Flag Too Soon. 12 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 INT_EARLY_VAL Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 16 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_EARLY_VAL Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 20 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 CLKRDY_IE Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock. 27 1 CLKRDY Clock Status. 28 1 WIN_EN Enables the Windowed Watchdog Function. 29 1 dis Windowed Mode Disabled (i.e. Compatibility Mode). 0 en Windowed Mode Enabled. 1 RST_EARLY Windowed Watchdog Timer Reset Flag Too Soon. 30 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST_LATE Windowed Watchdog Timer Reset Flag Too Late. 31 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST Windowed Watchdog Timer Reset Register. 0x04 write-only RESET Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled. 0 8 seq0 The first value to be written to reset the WDT. 0x000000A5 seq1 The second value to be written to reset the WDT. 0x0000005A CLKSEL Windowed Watchdog Timer Clock Select Register. 0x08 read-write SOURCE WWDT Clock Selection Register. 0 3 CNT Windowed Watchdog Timer Count Register. 0x0C read-only COUNT Current Value of the Windowed Watchdog Timer Counter. 0 32 WDT1 Windowed Watchdog Timer 1 0x40080800 WDT1 WDT1 IRQ 57 WUT 32-bit reloadable timer that can be used for timing and wakeup. 0x40006400 0x00 0x400 registers Wakeup_Timer WUT IRQ 53 CNT Count. This register stores the current timer count. 0x00 0x00000001 COUNT Timer Count Value. 0 32 CMP Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. 0x04 0x0000FFFF COMPARE Timer Compare Value. 0 32 INTR Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. 0x0C oneToClear IRQ_CLR Clear Interrupt. 0 1 CTRL Timer Control Register. 0x10 TMODE Timer Mode. 0 3 oneShot One Shot Mode. 0 continuous Continuous Mode. 1 counter Counter Mode. 2 capture Capture Mode. 4 compare Compare Mode. 5 gated Gated Mode. 6 captureCompare Capture/Compare Mode. 7 PRES Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. 3 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 TPOL Timer input/output polarity bit. 6 1 activeHi Active High. 0 activeLo Active Low. 1 TEN Timer Enable. 7 1 dis Disable. 0 en Enable. 1 PRES3 MSB of prescaler value. 8 1 NOLCMP Timer Non-Overlapping Compare Register. 0x14 NOLLCMP Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. 0 8 NOLHCMP Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. 8 8 PRESET Preset register. 0x18 PRESET Preset Value. 0 32 RELOAD Reload register. 0x1C RELOAD Rerload Value. 0 32 SNAPSHOT Snapshot register. 0x20 SNAPSHOT Snapshot Value. 0 32