Maxim-Integrated Maxim max32672 ARMCM4 1.0 MAX32672 High-Reliability, Tiny, Ultra-Low-Power AEM Cortex-M4F Microcontroller with 12-bit 1MSPS ADC. CM4 r2p1 little true true 3 false 8 32 0x20 read-write 0x00000000 0xFFFFFFFF ADC Inter-Integrated Circuit. ADC 0x40034000 32 0x00 0x1000 registers ADC ADC IRQ 20 CTRL0 Control Register 0. 0x00 ADC_EN ADC Enable. [0:0] read-write dis Disable ADC. 0 en enable ADC. 1 BIAS_EN Bias Enable. [1:1] read-write dis Disable Bias. 0 en Enable Bias. 1 SKIP_CAL Skip Calibration Enable. [2:2] read-write no_skip Do not skip calibration. 0 skip Skip calibration. 1 CHOP_FORCE Chop Force Control. [3:3] read-write dis Do not force chop mode. 0 en Force chop Mode. 1 RESETB Reset ADC. [4:4] read-write reset reset ADC. 0 activate activate ADC. 1 CTRL1 Control Register 1. 0x04 START Start conversion control. [0:0] read-write stop Stop conversions. 0 start Start conversions. 1 TRIG_MODE Trigger mode control. [1:1] read-write software software trigger mode. 0 hardware hardware trigger mode. 1 CNV_MODE Conversion mode control. [2:2] read-write atomic Do one conversion sequence. 0 continuous Do continuous conversion sequences. 1 SAMP_CK_OFF Sample clock off control. [3:3] read-write always Sample clock always generated. 0 cnv_only Sample clock generated only when converting. 1 TRIG_SEL Hardware trigger source select. [6:4] read-write TS_SEL Temp sensor select. [7:7] read-write dis Temp sensor is not one of the slots in the sequence. 0 en Temp sensor is one of the slots in the sequence. 1 AVG Number of samples to average for each output data code. [10:8] read-write avg1 1 Sample per output code. 0 avg2 2 Samples per output code. 1 avg4 4 Samples per output code. 2 avg8 8 Samples per output code. 3 avg16 16 Samples per output code. 4 avg32 32 Samples per output code. 5 NUM_SLOTS Number of slots enabled for the conversion sequence [20:16] read-write CLKCTRL Clock Control Register. 0x08 CLKSEL Clock source select. [1:0] read-write HCLK Select HCLK. 0 CLK_ADC0 Select CLK_ADC0. 1 CLK_ADC1 Select CLK_ADC1. 2 CLK_ADC2 Select CLK_ADC2. 3 CLKDIV Clock divider control. [6:4] read-write DIV2 Divide by 2. 0 DIV4 Divide by 4. 1 DIV8 Divide by 8. 2 DIV16 Divide by 16. 3 DIV1 Divide by 1. 4 SAMPCLKCTRL Sample Clock Control Register. 0x0C read-write TRACK_CNT Number of cycles for SAMPLE_CLK high time. [7:0] read-write IDLE_CNT Number of cycles for SAMPLE_CLK low time. [31:16] read-write CHSEL0 Channel Select Register 0. 0x10 slot0_id channel assignment for slot 0. [4:0] read-write slot1_id channel assignment for slot 1. [12:8] read-write slot2_id channel assignment for slot 2. [20:16] read-write slot3_id channel assignment for slot 3. [28:24] read-write CHSEL1 Channel Select Register 1. 0x14 slot4_id channel assignment for slot 4. [4:0] read-write slot5_id channel assignment for slot 5. [12:8] read-write slot6_id channel assignment for slot 6. [20:16] read-write slot7_id channel assignment for slot 7. [28:24] read-write CHSEL2 Channel Select Register 2. 0x18 slot8_id channel assignment for slot 8. [4:0] read-write slot9_id channel assignment for slot 9. [12:8] read-write slot10_id channel assignment for slot 10. [20:16] read-write slot11_id channel assignment for slot 11. [28:24] read-write CHSEL3 Channel Select Register 3. 0x1C slot12_id channel assignment for slot 12. [4:0] read-write slot13_id channel assignment for slot 13. [12:8] read-write slot14_id channel assignment for slot 14. [20:16] read-write slot15_id channel assignment for slot 15. [28:24] read-write RESTART Restart Count Control Register 0x30 CNT Number of sample periods to skip before restarting a continuous mode sequence [15:0] read-write DATAFMT Channel Data Format Register 0x3C MODE Data format control [31:0] read-write FIFODMACTRL FIFO and DMA control 0x40 DMA_EN DMA Enable. [0:0] read-write dis Disable DMA. 0 en Enable DMA. 1 FLUSH FIFO Flush. [1:1] read-write normal Normal FIFO operation. 0 flush Flush FIFO. 1 DATA_FORMAT DATA format control. [3:2] read-write data_status Data and Status in FIFO. 0 data_only Only Data in FIFO. 1 raw_data_only Only Raw Data in FIFO. 2 THRESH FIFO Threshold. These bits define the FIFO interrupt threshold. [15:8] read-write DATA Data Register (FIFO). 0x44 DATA Conversion data. [15:0] read-only CHAN Channel for the data. [20:16] read-only INVALID Invalid status for the data. [24:24] read-only CLIPPED Clipped status for the data. [31:31] read-only STATUS Status Register 0x48 READY Indication that the ADC is in ON power state [0:0] read-only EMPTY FIFO Empty [1:1] read-only FULL FIFO full [2:2] read-only FIFO_LEVEL Number of entries in FIFO available to read [15:8] read-only CHSTATUS Channel Status 0x4C CLIPPED [31:0] read-write INTEN Interrupt Enable Register. 0x50 READY ADC is ready. [0:0] read-write ABORT Conversion start is aborted. [2:2] read-write START_DET Conversion start is detected. [3:3] read-write SEQ_STARTED [4:4] read-write SEQ_DONE [5:5] read-write CONV_DONE [6:6] read-write CLIPPED [7:7] read-write FIFO_LVL [8:8] read-write FIFO_UFL [9:9] read-write FIFO_OFL [10:10] read-write INTFL Interrupt Flags Register. 0x54 READY ADC is ready. [0:0] read-write oneToClear ABORT Conversion start is aborted. [2:2] read-write oneToClear START_DET Conversion start is detected. [3:3] read-write oneToClear SEQ_STARTED [4:4] read-write oneToClear SEQ_DONE [5:5] read-write oneToClear CONV_DONE [6:6] read-write oneToClear CLIPPED [7:7] read-write oneToClear FIFO_LVL [8:8] read-write oneToClear FIFO_UFL [9:9] read-write oneToClear FIFO_OFL [10:10] read-write oneToClear SFRADDROFFSET SFR Address Offset Register 0x60 OFFSET Address Offset for SAR Digital [7:0] read-write SFRADDR SFR Address Register 0x64 ADDR Address to SAR Digital [7:0] read-write SFRWRDATA SFR Write Data Register 0x68 DATA DATA to SAR Digital [7:0] read-write SFRRDDATA SFR Read Data Register 0x6C DATA DATA from SAR Digital [7:0] read-only SFRSTATUS SFR Status Register 0x70 NACK NACK status for SAR Digital SFR communication [0:0] read-only AES AES Keys. 0x40207400 0x00 0x400 registers CTRL AES Control Register 0x0000 32 EN AES Enable [0:0] read-write DMA_RX_EN DMA Request To Read Data Output FIFO [1:1] read-write DMA_TX_EN DMA Request To Write Data Input FIFO [2:2] read-write START Start AES Calculation [3:3] read-write INPUT_FLUSH Flush the data input FIFO [4:4] read-write OUTPUT_FLUSH Flush the data output FIFO [5:5] read-write KEY_SIZE Encryption Key Size [7:6] read-write AES128 128 Bits. 0 AES192 192 Bits. 1 AES256 256 Bits. 2 TYPE Encryption Type Selection [9:8] read-write STATUS AES Status Register 0x0004 BUSY AES Busy Status [0:0] read-write INPUT_EM Data input FIFO empty status [1:1] read-write INPUT_FULL Data input FIFO full status [2:2] read-write OUTPUT_EM Data output FIFO empty status [3:3] read-write OUTPUT_FULL Data output FIFO full status [4:4] read-write INTFL AES Interrupt Flag Register 0x0008 DONE AES Done Interrupt [0:0] read-write KEY_CHANGE External AES Key Changed Interrupt [1:1] read-write KEY_ZERO External AES Key Zero Interrupt [2:2] read-write OV Data Output FIFO Overrun Interrupt [3:3] read-write KEY_ONE KEY_ONE [4:4] read-write INTEN AES Interrupt Enable Register 0x000C DONE AES Done Interrupt Enable [0:0] read-write KEY_CHANGE External AES Key Changed Interrupt Enable [1:1] read-write KEY_ZERO External AES Key Zero Interrupt Enable [2:2] read-write OV Data Output FIFO Overrun Interrupt Enable [3:3] read-write KEY_ONE KEY_ONE [4:4] read-write FIFO AES Data Register 0x0010 DATA AES FIFO [0:0] read-write SYS_AESKEYS System AES Key Registers. 0x40205000 0x00 0x400 registers KEY0 AES Key 0. 0x00 32 KEY1 AES Key 1. 0x04 32 KEY2 AES Key 2. 0x08 32 KEY3 AES Key 3. 0x0C 32 KEY4 AES Key 4. 0x10 32 KEY5 AES Key 5. 0x14 32 KEY6 AES Key 6. 0x18 32 KEY7 AES Key 7. 0x1C 32 USR_AESKEYS User AES Key Registers. 0x40005000 0x00 0x400 registers SRAM_KEY AES SRAM KEY 0x00 32 CODE_KEY AES CODE Key 0x20 DATA_KEY AES DATA KEY 0x40 CTB The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. 0x40001000 0x00 0x1000 registers Crypto_Engine Crypto Engine interrupt. 27 CTRL Crypto Control Register. 0x00 0xC0000000 RST Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle. 0 1 reset_write write reset Starts reset operation. 1 reset_read read reset_done Reset complete. 0 busy Reset in progress. 1 INTR Interrupt Enable. Generates an interrupt when done or error set. 1 1 dis Disable 0 en Enable 1 SRC Source Select. This bit selects the hash function and CRC generator input source. 2 1 inputFIFO Input FIFO 0 outputFIFO Output FIFO 1 BSO Byte Swap Output. Note. No byte swap will occur if there is not a full word. 4 1 BSI Byte Swap Input. Note. No byte swap will occur if there is not a full word. 5 1 WAIT_EN Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready. 6 1 WAIT_POL Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state. 7 1 activeLo Active Low. 0 activeHi Active High. 1 WRSRC Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled. 8 2 none None. 0 cipherOutput Cipher Output. 1 readFIFO Read FIFO. 2 RDSRC Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator. 10 2 dmaDisabled DMA Disable. 0 dmaOrApb DMA Or APB. 1 rng RNG. 2 FLAG_MODE Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs. 14 1 unres_wr Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags. 0 res_wr Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect. 1 DMADNEMSK DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA. 15 1 not_used DMA_DONE not used in setting CRYPTO_CTRL.DONE bit. 0 used DMA_DONE used in setting CRYPTO_CTRL.DONE bit. 1 DMA_DONE DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation. 24 1 notDone Not Done. 0 done Done. 1 GLS_DONE Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator. 25 1 HSH_DONE Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation. 26 1 CPH_DONE Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation. 27 1 ERR AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block. 29 1 read-only noError No Error. 0 error Error. 1 RDY Ready. Crypto block ready for more data. 30 1 read-only busy Busy. 0 ready Ready. 1 DONE Done. One or more cryptographic calculations complete (logical OR of done flags). 31 1 read-only CIPHER_CTRL Cipher Control Register. 0x04 ENC Encrypt. Select encryption or decryption of input data. 0 1 encrypt Encrypt. 0 decrypt Decrypt. 1 KEY Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag. 1 1 complete No operation/complete. 0 start Start operation. 1 SRC Source of Random key. 2 2 cipherKey User cipher key (0x4000_1060). 0 regFile Key from battery-backed register file (0x4000_5000 to 0x4000_501F). 2 qspiKey_regFile Key from battery-backed register file (0x4000_5020 to 0x4000_502F). 3 CIPHER Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation. 4 3 dis Disabled. 0 aes128 AES 128. 1 aes192 AES 192. 2 aes256 AES 256. 3 des DES. 4 tdes Triple DES. 5 MODE Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes. 8 3 ECB ECB Mode. 0 CBC CBC Mode. 1 CFB CFB (AES only). 2 OFB OFB (AES only). 3 CTR CTR (AES only). 4 HVC H Vector Computation. 11 1 read-only DTYPE GCM/CCM data type. 12 1 read-only CCMM CCM M Parameter. 13 3 read-only CCML CCM L Parameter. 16 3 read-only HASH_CTRL HASH Control Register. 0x08 INIT Initialize. Initializes hash registers with standard constants. 0 1 nop No operation/complete. 0 start Start operation. 1 XOR XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad. 1 1 dis Disable. 0 en Enable. 1 HASH Hash function selection. 2 3 dis Disabled. 0 sha1 SHA-1. 1 sha224 SHA 224. 2 sha256 SHA 256. 3 sha384 SHA 384. 4 sha512 SHA 512. 5 LAST Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash. 5 1 noEffect No Effect. 0 lastMsgData Last Message Data. 1 CRC_CTRL CRC Control Register. 0x0C CRC Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled. 0 1 dis Disable. 0 en Enable. 1 MSB MSB select. This bit selects the order of calculating CRC on data. 1 1 lsbFirst LSB First. 0 msbFirst MSB First. 1 PRNG Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle. 2 1 ENT Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source. 3 1 HAM Hamming Code Enable. Enable hamming code calculation. 4 1 HRST Hamming Reset. Reset Hamming code ECC generator for next block. 5 1 write-only write reset Starts reset operation. 1 DMA_SRC Crypto DMA Source Address. 0x10 ADDR DMA Source Address. 0 32 DMA_DEST Crypto DMA Destination Address. 0x14 ADDR DMA Destination Address. 0 32 DMA_CNT Crypto DMA Byte Count. 0x18 ADDR DMA Byte Address. 0 32 4 4 DIN[%s] Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register. 0x20 write-only DATA Crypto Data Input. Input can be written to this register instead of using DMA. 0 32 4 4 DOUT[%s] Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits. 0x30 read-only DATA Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm. 0 32 CRC_POLY CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. 0x40 0xEDB88320 POLY CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. 0 32 CRC_VAL CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit. 0x44 0xFFFFFFFF VAL CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit. 0 32 HAM_ECC Hamming ECC Register. 0x4C ECC Hamming ECC Value. These bits are the even parity of their corresponding bit groups. 0 16 PAR Parity. This is the parity of the entire array. 16 1 even Even. 0 odd Odd. 1 4 4 CIPHER_INIT[%s] Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. 0x50 IVEC Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. 0 32 8 4 CIPHER_KEY[%s] Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits. 0x60 write-only KEY Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits. 0 32 16 4 HASH_DIGEST[%s] This register holds the calculated hash value. This register is affected by the endian swap bits. 0x80 HASH This register holds the calculated hash value. This register is affected by the endian swap bits. 0 32 4 4 HASH_MSG_SZ[%s] Message Size. This register holds the lowest 32-bit of message size in bytes. 0xC0 MSGSZ Message Size. This register holds the lowest 32-bit of message size in bytes. 0 32 2 4 AAD_LENGTH[%s] AAD Length Registers. 0xD0 0x0 LENGTH AAD length in bytes for AES GCM and CCM operations. 0 32 2 4 PLD_LENGTH[%s] PLD Length Registers. 0xD8 0x0 LENGTH PLD length in bytes for AES GCM and CCM operations. 0 32 4 4 TAGMIC[%s] TAG/MIC Registers. 0xE0 LENGTH TAG/MIC output for AES GCM and CCM operations. 0 32 SCA_CTRL0 SCA Control 0 Register. 0x100 STC Start Calculation. 0 1 SCAIE SCA Interrupt Enable. 1 1 disable Disable 0 enable Enable 1 ABORT Abort Operation. 2 1 ERMEM Erase Cryptographic Memory. 4 1 MANPARAM ECC Parameter Source. 5 1 HWKEY Hardware Key Select. 6 1 OPCODE SCA Opcode. 8 5 MODADDR MODULO Address Offset. 16 5 ECCSIZE ECC Size. 24 2 SCA_CTRL1 SCA Control 1 Register. 0x104 MAN SCA Mode. 0 1 auto Auto Mode 0 manual Manual Mode 1 AUTOCARRY Automatically propagate the carry for the next operation. 1 1 PLUSONE Enable Carry propagation for the next operation. 2 1 NRNG NRNG. 5 1 CARRYPOS To set Carry location. 8 10 SCA_STAT SCA Status Register. 0x108 BUSY SCA Busy. 0 1 SCAIF SCA Interrupt Flag. 1 1 PVF1 Point 1 Verification Failed. 2 1 PVF2 Point 2 Verification Failed. 3 1 FSMERR FSM Transition Error. 4 1 COMPERR EC Computation Error. 5 1 MEMERR SCA Memory Access Error. 6 1 CARRY Carry on ongoing operation. 8 1 GTE2I2 Modulo 2x Result. 9 1 ALUNEG1 ALU 2 SubSign of the subtraction result for ALU_2. 10 1 ALUNEG2 ALU 2 SubSign of the subtraction result for ALU_2. 11 1 SCA_PPX_ADDR PPX Coordinate Data Pointer Register. 0x10C 0x0 ADDR Point P Coordinate Data Pointer. 0 32 SCA_PPY_ADDR PPY Coordinate Data Pointer Register. 0x110 0x0 ADDR Point P Coordinate Data Pointer. 0 32 SCA_PPZ_ADDR PPZ Coordinate Data Pointer Register. 0x114 0x0 ADDR Point P Coordinate Data Pointer. 0 32 SCA_PQX_ADDR PQX Coordinate Data Pointer Register. 0x118 0x0 ADDR Point Q Coordinate Data Pointer. 0 32 SCA_PQY_ADDR PQY Coordinate Data Pointer Register. 0x11C 0x0 ADDR Point Q Coordinate Data Pointer. 0 32 SCA_PQZ_ADDR PQZ Coordinate Data Pointer Register. 0x120 0x0 ADDR Point Q Coordinate Data Pointer. 0 32 SCA_RDSA_ADDR SCA RDSA Address Register. 0x124 0x0 ADDR The starting address of the R portion for R, S ECDSA signature. 0 32 SCA_RES_ADDR SCA Result Address Register. 0x128 0x0 ADDR Starting address of result storage. 0 32 SCA_OP_BUFF_ADDR SCA Operation Buffer Address Register. 0x12C 0x0 ADDR Starting address of operation buffer. 0 32 SCA_MODDATA SCA Modulo Data Input Register. 0x130 0x0 DATA Used to load the SCA modulo for modular operations. 0 32 SCA_NRNG Starting address for NRNG stored in SRAM. 0x134 0x0 DMA DMA Controller Fully programmable, chaining capable DMA channels. 0x40028000 32 0x00 0x1000 registers DMA0 28 DMA1 29 DMA2 30 DMA3 31 DMA4 68 DMA5 69 DMA6 70 DMA7 71 DMA8 72 DMA9 73 DMA10 74 DMA11 75 INTEN DMA Control Register. 0x000 CH0 Channel 0 Interrupt Enable. 0 1 dis Disable. 0 en Enable. 1 CH1 Channel 1 Interrupt Enable. 1 1 CH2 Channel 2 Interrupt Enable. 2 1 CH3 Channel 3 Interrupt Enable. 3 1 CH4 Channel 4 Interrupt Enable. 4 1 CH5 Channel 5 Interrupt Enable. 5 1 CH6 Channel 6 Interrupt Enable. 6 1 CH7 Channel 7 Interrupt Enable. 7 1 INTFL DMA Interrupt Register. 0x004 read-only CH0 Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CH1 1 1 CH2 2 1 CH3 3 1 CH4 4 1 CH5 5 1 CH6 6 1 CH7 7 1 12 0x20 CH[%s] DMA Channel registers. dma_ch 0x100 read-write CTRL DMA Channel Control Register. 0x000 EN Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 RLDEN Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. 1 1 dis Disable. 0 en Enable. 1 PRI DMA Priority. 2 2 high Highest Priority. 0 medHigh Medium High Priority. 1 medLow Medium Low Priority. 2 low Lowest Priority. 3 REQUEST Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. 4 6 MEMTOMEM Memory To Memory 0x00 SPI0RX SPI0 RX 0x01 SPI1RX SPI1 RX 0x02 SPI2RX SPI2 RX 0x03 UART0RX UART0 RX 0x04 UART1RX UART1 RX 0x05 I2C0RX I2C0 RX 0x07 I2C1RX I2C1 RX 0x08 ADC ADC 0x09 I2C2RX I2C2 RX 0x0A UART2RX UART2 RX 0x0E SPI3RX SPI3 RX 0x0F AESRX AES RX 0x10 UART3RX UART3 RX 0x1C I2SRX I2S RX 0x1E SPI0TX SPI0 TX 0x21 SPI1TX SPI1 TX 0x22 SPI2TX SPI2 TX 0x23 UART0TX UART0 TX 0x24 UART1TX UART1 TX 0x25 I2C0TX I2C0 TX 0x27 I2C1TX I2C1 TX 0x28 I2C2TX I2C2 TX 0x2A CRCTX CRC TX 0x2C UART2TX UART2 TX 0x2E SPI3TX SPI3 TX 0x2F AESTX AES TX 0x30 UART3TX UART3 TX 0x3C I2STX I2S TX 0x3E TO_WAIT Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. 10 1 dis Disable. 0 en Enable. 1 TO_PER Timeout Period Select. 11 3 to4 Timeout of 3 to 4 prescale clocks. 0 to8 Timeout of 7 to 8 prescale clocks. 1 to16 Timeout of 15 to 16 prescale clocks. 2 to32 Timeout of 31 to 32 prescale clocks. 3 to64 Timeout of 63 to 64 prescale clocks. 4 to128 Timeout of 127 to 128 prescale clocks. 5 to256 Timeout of 255 to 256 prescale clocks. 6 to512 Timeout of 511 to 512 prescale clocks. 7 TO_CLKDIV Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. 14 2 dis Disable timer. 0 div256 hclk / 256. 1 div64k hclk / 64k. 2 div16M hclk / 16M. 3 SRCWD Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. 16 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 SRCINC Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. 18 1 dis Disable. 0 en Enable. 1 DSTWD Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). 20 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 DSTINC Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. 22 1 dis Disable. 0 en Enable. 1 BURST_SIZE Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. 24 5 DIS_IE Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. 30 1 dis Disable. 0 en Enable. 1 CTZ_IE Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. 31 1 dis Disable. 0 en Enable. 1 STATUS DMA Channel Status Register. 0x004 STATUS Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). 0 1 read-only dis Disable. 0 en Enable. 1 IPEND Channel Interrupt. 1 1 read-only inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CTZ_IF Count-to-Zero (CTZ) Interrupt Flag 2 1 oneToClear RLD_IF Reload Event Interrupt Flag. 3 1 oneToClear BUS_ERR Bus Error. Indicates that an AHB abort was received and the channel has been disabled. 4 1 oneToClear TO_IF Time-Out Event Interrupt Flag. 6 1 oneToClear SRC Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. 0x008 ADDR 0 32 DST Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. 0x00C ADDR 0 32 CNT DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. 0x010 CNT DMA Counter. 0 24 SRCRLD Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. 0x014 ADDR Source Address Reload Value. 0 31 DSTRLD Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. 0x018 ADDR Destination Address Reload Value. 0 31 CNTRLD DMA Channel Count Reload Register. 0x01C CNT Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. 0 24 EN Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. 31 1 dis Disable. 0 en Enable. 1 FCR Function Control Register. 0x40000800 0x00 0x400 registers FCTRL0 Register 0. 0x00 read-write ERFO_RANGE_SEL 14MHz-32MHz ERFO Frequency Range Select. 0 3 KEYWIPE_SYS KEYWIPE_SYS. 8 1 I2C0_SDA_FILTER_EN I2C0 SDA Glitch Filter Enable. 20 1 dis Filter disabled. 0 en Filter enabled. 1 I2C0_SCL_FILTER_EN I2C0 SCL Glitch Filter Enable. 21 1 I2C1_SDA_FILTER_EN I2C1 SDA Glitch Filter Enable. 22 1 I2C1_SCL_FILTER_EN I2C1 SCL Glitch Filter Enable. 23 1 I2C2_SDA_FILTER_EN I2C2 SDA Glitch Filter Enable. 24 1 I2C2_SCL_FILTER_EN I2C2 SCL Glitch Filter Enable. 25 1 AUTOCAL0 Register 1. 0x04 read-write SEL Auto-calibration Enable. 0 1 dis Disabled. 0 en Enabled. 1 EN Autocalibration Run. 1 1 not Not Running. 0 run Running. 1 LOAD Load Trim. 2 1 INVERT Invert Gain. 3 1 not do Not invert trim step. 0 invert Invert trim step. 1 ATOMIC Atomic mode. 4 1 not Not Running. 0 run Running. 1 GAIN MU value. 8 12 TRIM 150MHz HFIO Auto Calibration Trim 23 9 AUTOCAL1 Register 2. 0x08 read-write INITIAL 100MHz IPO Trim Automatic Calibration Initial Trim. 0 9 AUTOCAL2 Register 3. 0x0C read-write RUNTIME 100MHz IPO Trim Automatic Calibration Run Time. 0 8 DIV 100MHz IPO Trim Automatic Calibration Divide Factor. 8 13 TS0 Register 4. 0x10 read-only GAIN Unsigned gain for temp sensor normalization 0 12 TS1 Register 5. 0x14 read-only OFFSET Signed offset for temp sensor correction 0 32 ADCREFTRIM0 ADC Reference Trim 0 0x18 read-write VREFP Trimming code for VREFP output of reference buffer 0 7 VREFM Trimming code for VREFM output of reference buffer 8 7 VCM Trimming code for VCM output of reference buffer 16 2 VX2_TUNE Controls tuning capacitor in fine DAC (offset binary) 24 6 ADCREFTRIM1 ADC Reference Trim 1 0x1C read-write VREFP Trimming code for VREFP output of reference buffer 0 7 VREFM Trimming code for VREFM output of reference buffer 8 7 VCM Trimming code for VCM output of reference buffer 16 2 VX2_TUNE Controls tuning capacitor in fine DAC (offset binary) 24 6 ADCREFTRIM2 ADC Reference Trim 2 0x20 read-write IDRV_1P25 Trimming code for reference buffer drive strength. 1.25V 0 4 IBOOST_1P25 Trimming value for extra drive current in reference buffer outputs. 2.048V 4 1 IDRV_2P048 Trimming code for reference buffer drive strength. 2.048V 8 4 IBOOST_2P048 Trimming value for extra drive current in reference buffer outputs. 2.048V 12 1 VCM Trimming code for VCM output of reference buffer 16 2 VX2_TUNE Controls tuning capacitor in fine DAC (offset binary) 24 6 ERFOKS External Radio Frequency Oscillator Kick Start Control Register. 0x24 read-write CTRL Kickstart Control for ERFO. 0 16 FLC Flash Memory Control. FLSH_ 0x40029000 0x00 0x400 registers Flash_Controller Flash Controller interrupt. 23 ADDR Flash Write Address. 0x00 ADDR Address for next operation. 0 32 CLKDIV Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. 0x04 0x00000064 CLKDIV Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. 0 8 CTRL Flash Control Register. 0x08 WR Write. This bit is automatically cleared after the operation. 0 1 complete No operation/complete. 0 start Start operation. 1 ME Mass Erase. This bit is automatically cleared after the operation. 1 1 PGE Page Erase. This bit is automatically cleared after the operation. 2 1 ERASE_CODE Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. 8 8 nop No operation. 0 erasePage Enable Page Erase. 0x55 eraseAll Enable Mass Erase. The debug port must be enabled. 0xAA PEND Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. 24 1 read-only idle Idle. 0 busy Busy. 1 LVE Low Voltage enable. 25 1 UNLOCK Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. 28 4 unlocked Flash Unlocked. 2 locked Flash Locked. 3 INTR Flash Interrupt Register. 0x024 DONE Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 AF Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. 1 1 noError No Failure. 0 error Failure occurs. 1 DONEIE Flash Done Interrupt Enable. 8 1 disable Disable. 0 enable Enable. 1 AFIE 9 1 ECCDATA ECC Data Register. 0x2C EVEN Error Correction Code Odd Data. 0 9 ODD Error Correction Code Even Data. 16 9 4 4 DATA[%s] Flash Write Data. 0x30 DATA Data next operation. 0 32 ACTRL Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. 0x40 write-only ACTRL Access control. 0 32 WELR0 WELR0 0x80 WELR0 Access control. 0 32 WELR1 WELR1 0x88 WELR1 Access control. 0 32 RLR0 RLR0 0x90 RLR0 Access control. 0 32 RLR1 RLR1 0x98 RLR1 Access control. 0 32 FLC1 Flash Memory Control. 1 0x40029400 FLC1 FLC1 IRQ 87 GCR Global Control Registers. 0x40000000 0 0x400 registers SYSCTRL System Control. 0x00 0xFFFFFFFE SBUSARB System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. 1 2 Fix Fixed Burst abritration. 0 Round Round-robin scheme. 1 FLASH_PAGE_FLIP . 4 1 dis Physical layout matches logical layout. 0 en Bottom half mapped to logical top half and vice versa. 1 FPU_DIS Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4 5 1 en FPU Enabled. 0 dis FPU Disabled. 1 ICC0_FLUSH Internal Cache Controller Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 SWD_DIS Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set) 14 1 en SWD Enabled. 0 dis SWD Disabled. 1 CHKRES ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 RST0 Reset. 0x04 DMA DMA Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 WDT0 Watchdog Timer Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 TMR0 Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TMR1 Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TMR2 Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TMR3 Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 UART0 UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI0 SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 SPI1 SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 14 1 SPI2 SPI2 Reset. Setting this bit to 1 resets all SPI 1 blocks. 15 1 I2C0 I2C0 Reset. 16 1 CTB Crypto Toolbox Reset. 18 1 TRNG TRNG Reset. 24 1 ADC ADC Reset. 26 1 UART2 UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. 28 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLKCTRL Clock Control. 0x08 0x00000008 SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSCLK_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 ERFO 32MHz Crystal is used for the system clock. 2 INRO 80kHz LIRC is used for the system clock. 3 IPO The internal 96 MHz oscillator is used for the system clock. 4 IBRO The internal 8 MHz oscillator is used for the system clock. 5 ERTCO 32kHz is used for the system clock. 6 EXTCLK External clock on gpio0 28 (AF4). 7 SYSCLK_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 IPO_DIV Divides the HIRC96M clock before the system clock prescaler, will affect HIRC96M Autocalibration. 14 2 div1 divide clock by 1 0 div2 divide clock by 2 1 div4 divide clock by 4 2 div8 divide clock by 8 3 ERFO_EN 32MHz Crystal Oscillator Enable. 16 1 dis Is Disabled. 0 en Is Enabled. 1 IPO_EN 96MHz High Frequency Internal Reference Clock Enable. 19 1 IBRO_EN 8MHz High Frequency Internal Reference Clock Enable. 20 1 IBRO_VS 8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M. 21 1 1V Dedicated 1v regulated supply. 0 Vcor VCore Supply 1 ERFO_RDY 32MHz Crystal Oscillator Ready 24 1 read-only busy Is not Ready. 0 ready Is Ready. 1 ERTCO_RDY 32kHz Crystal Oscillator Ready 25 1 read-only busy Is not Ready. 0 ready Is Ready. 1 IPO_RDY 96MHz HIRC Ready. 27 1 IBRO_RDY 8MHz HIRC Ready. 28 1 INRO_RDY 8kHz Low Frequency Reference Clock Ready. 29 1 EXTCLK_RDY External Clock (GPIO0[11] AF2) 31 1 PM Power Management. 0x0C MODE Operating Mode. This three bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 shutdown Shutdown Mode. 3 backup Backup Mode. 4 GPIO_WE GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 dis Wake Up Disable. 0 en Wake Up Enable. 1 RTC_WE RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. 5 1 LPTMR0_WE TIMER4 Wake Up Enable. This bit enables TIMER4 as wakeup source. 6 1 LPTMR1_WE TIMER5 Wake Up Enable. This bit enables TIMER5 as wakeup source. 7 1 LPUART0_WE LPUART3 Wake Up Enable. This bit enables LPUART3 as wakeup source. 8 1 AINCOMP_WE AINCOMP Wake Up Enable. This bit enables AINCOMP as wakeup source. 9 1 ERFO_PD 32MHz power down. This bit selects 32MHz Crystal power state in DEEPSLEEP mode. 12 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 IPO_PD 96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode. 16 1 IBRO_PD 8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode. 17 1 ERFO_BP 32MHz Oscillator Bypass 20 1 dis Bypass Disabled. 0 en Bypass Enabled. 1 PCLKDIV Peripheral Clock Divider. 0x18 0x00000001 AON_CLKDIV Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider 0 3 div4 0 div8 1 div16 2 div32 3 DIV_CLK_OUT_CTRL DIV_CLK_OUT Control 14 2 off HART clock off. 0 div2 HART clock HIRC8M Div 2. 1 div4 HART clock XO32M Div 4. 2 div8 HART clock XO32M Div 8. 3 DIV_CLK_OUT_EN DIV_CLK_OUT Enable 16 1 dis HART clock Disable. 0 en HART clock Enable. 1 PCLKDIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Disable. 1 1 DMA DMA Disable. 5 1 SPI0 SPI 0 Disable. 6 1 SPI1 SPI 1 Disable. 7 1 SPI2 SPI 2 Disable. 8 1 UART0 UART 0 Disable. 9 1 UART1 UART 1 Disable. 10 1 I2C0 I2C 0 Disable. 13 1 CTB Crypto Disable. 14 1 TMR0 Timer 0 Disable. 15 1 TMR1 Timer 1 Disable. 16 1 TMR2 Timer 2 Disable. 17 1 TMR3 Timer 3 Disable. 18 1 ADC ADC Clock Disable. 23 1 I2C1 I2C 1 Disable. 28 1 MEMCTRL Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. 0 3 RAMWS_EN System RAM Wait State enable 4 1 no no SRAM wait state. 0 en SRAM wait state enabled. 1 RAM0LS_EN System RAM 0 Light Sleep Mode. 8 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 RAM1LS_EN System RAM 1 Light Sleep Mode. 9 1 RAM2LS_EN System RAM 2 Light Sleep Mode. 10 1 RAM3LS_EN System RAM 3 Light Sleep Mode. 11 1 ICC0LS_EN ICache RAM Light Sleep Mode. 12 1 ROMLS_EN ROM Light Sleep Mode. 13 1 MEMZ Memory Zeroize Control. 0x2C RAM0 System RAM 0 Block. 0 1 nop No operation/complete. 0 start Start operation. 1 RAM1 System RAM 1 zeroization. 1 1 RAM2 System RAM 2 zeroization. 2 1 RAMCB System RAM check bit zeroization. 3 1 ICC0 Instruction Cache. 4 1 SYSST System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 reset Reset. 1 reset_done Reset complete. 0 WDT1 WDT1 Reset. 8 1 AES WDT1 Reset. 10 1 AC AC Reset. 14 1 I2C2 I2C2 Reset. 17 1 I2S I2S Reset. 23 1 QDEC QDEC Reset. 25 1 PCLKDIS1 Peripheral Clock Disable. 0x48 UART2 UART2 Disable. 1 1 en Enable. 0 dis Disable. 1 TRNG TRNG Disable. 2 1 WDT0 WDT0 Disable. 4 1 WDT1 WDT1 Disable. 5 1 ICC0 ICACHE Disable. 11 1 AES AES Clock Disable. 15 1 I2C2 I2C2 Disable. 21 1 I2S I2S Clock Disable. 23 1 QDEC Quadrature Decoder Interface Clock Disable. 25 1 EVENTEN Event Enable Register. 0x4C DMA Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 dis Event Disable. 0 en Event Enable. 1 RX Enable RXEV pin event. When this bit is set, a logic high of GPIO0[20] (AF1) will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 dis Event Disable. 0 en Event Enable. 1 TX Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[21] (AF1). 2 1 dis Event Disable. 0 en Event Enable. 1 REVISION Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYSIE System Status Interrupt Enable Register. 0x54 ICEUNLOCK ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 ECCERR ECC Error Register 0x64 RAM0_1 ECC System RAM0 and RAM1 Error Flag. Write 1 to clear. 0 1 RAM2 ECC System RAM2 Error Flag. Write 1 to clear. 1 1 RAM3 ECC System RAM3 Error Flag. Write 1 to clear. 2 1 ICC0 ECC Icache Error Flag. Write 1 to clear. 3 1 FLASH0 ECC Flash0 Error Flag. Write 1 to clear. 4 1 FLASH1 ECC Flash1 Error Flag. Write 1 to clear. 5 1 ECCCED ECC Correctable Error Detect Register 0x68 RAM0_1 ECC System RAM0 and RAM1 Error Flag. Write 1 to clear. 0 1 RAM2 ECC System RAM2 Error Flag. Write 1 to clear. 1 1 RAM3 ECC System RAM3 Error Flag. Write 1 to clear. 2 1 ICC0 ECC Icache Error Flag. Write 1 to clear. 3 1 FLASH0 ECC Flash0 Error Flag. Write 1 to clear. 4 1 FLASH1 ECC Flash1 Error Flag. Write 1 to clear. 5 1 ECCIE ECC IRQ Enable Register 0x6C RAM0_1 ECC System RAM0 and RAM1 Error interrupt enable. 0 1 dis interrupt disabled. 0 en interrupt enabled. 1 RAM2 ECC System RAM2 Error interrupt enable. 1 1 RAM3 ECC System RAM3 Error interrupt enable. 2 1 ICC0 ECC Icache Error interrupt enable. 3 1 FLASH0 ECC Flash0 Error interrupt enable. 4 1 FLASH1 ECC Flash1 Error interrupt enable. 5 1 ECCADDR ECC Error Address Register 0x70 DATARAMADDR ECC Error Address/TAG RAM Error Address. 0 14 DATARAMBANK ECC Error Address/DATA RAM Error Bank. 14 1 DATARAMERR ECC Error Address/DATA RAM Error Address. 15 1 TAGRAMADDR ECC Error Address/TAG RAM Error Address. 16 14 TAGRAMBANK ECC Error Address/TAG RAM Error Bank. 30 1 TAGRAMERR ECC Error Address/TAG RAM Error. 31 1 GPIO0 Individual I/O for each GPIO GPIO 0x40008000 0x00 0x1000 registers GPIO0 GPIO0 interrupt. 24 EN0 GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. 0x00 GPIO_EN Mask of all of the pins on the port. 0 32 ALTERNATE Alternate function enabled. 0 GPIO GPIO function is enabled. 1 EN0_SET GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. 0x04 ALL Mask of all of the pins on the port. 0 32 EN0_CLR GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. 0x08 ALL Mask of all of the pins on the port. 0 32 OUTEN GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. 0x0C EN Mask of all of the pins on the port. 0 32 dis GPIO Output Disable 0 en GPIO Output Enable 1 OUTEN_SET GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. 0x10 ALL Mask of all of the pins on the port. 0 32 OUTEN_CLR GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. 0x14 ALL Mask of all of the pins on the port. 0 32 OUT GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. 0x18 GPIO_OUT Mask of all of the pins on the port. 0 32 low Drive Logic 0 (low) on GPIO output. 0 high Drive logic 1 (high) on GPIO output. 1 OUT_SET GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. 0x1C write-only GPIO_OUT_SET Mask of all of the pins on the port. 0 32 no No Effect. 0 set Set GPIO_OUT bit in this position to '1' 1 OUT_CLR GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. 0x20 write-only GPIO_OUT_CLR Mask of all of the pins on the port. 0 32 IN GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. 0x24 read-only GPIO_IN Mask of all of the pins on the port. 0 32 INTMODE GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. 0x28 GPIO_INTMODE Mask of all of the pins on the port. 0 32 level Interrupts for this pin are level triggered. 0 edge Interrupts for this pin are edge triggered. 1 INTPOL GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. 0x2C GPIO_INTPOL Mask of all of the pins on the port. 0 32 falling Interrupts are latched on a falling edge or low level condition for this pin. 0 rising Interrupts are latched on a rising edge or high condition for this pin. 1 INEN GPIO Input Enable 0x30 INTEN GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. 0x34 GPIO_INTEN Mask of all of the pins on the port. 0 32 dis Interrupts are disabled for this GPIO pin. 0 en Interrupts are enabled for this GPIO pin. 1 INTEN_SET GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. 0x38 GPIO_INTEN_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set GPIO_INT_EN bit in this position to '1' 1 INTEN_CLR GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. 0x3C GPIO_INTEN_CLR Mask of all of the pins on the port. 0 32 no No Effect. 0 clear Clear GPIO_INT_EN bit in this position to '0' 1 INTFL GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. 0x40 read-only GPIO_INTFL Mask of all of the pins on the port. 0 32 no No Interrupt is pending on this GPIO pin. 0 pending An Interrupt is pending on this GPIO pin. 1 INTFL_CLR GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. 0x48 ALL Mask of all of the pins on the port. 0 32 WKEN GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. 0x4C GPIO_WKEN Mask of all of the pins on the port. 0 32 dis PMU wakeup for this GPIO is disabled. 0 en PMU wakeup for this GPIO is enabled. 1 WKEN_SET GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. 0x50 ALL Mask of all of the pins on the port. 0 32 WKEN_CLR GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. 0x54 ALL Mask of all of the pins on the port. 0 32 DUALEDGE GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. 0x5C GPIO_DUALEDGE Mask of all of the pins on the port. 0 32 no No Effect. 0 en Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. 1 PADCTRL0 GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x60 GPIO_PADCTRL0 The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Weak pull-up mode. 1 pd weak pull-down mode. 2 PADCTRL1 GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x64 GPIO_PADCTRL1 The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Weak pull-up mode. 1 pd weak pull-down mode. 2 EN1 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x68 GPIO_EN1 Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 EN1_SET GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. 0x6C ALL Mask of all of the pins on the port. 0 32 EN1_CLR GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. 0x70 ALL Mask of all of the pins on the port. 0 32 EN2 GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x74 GPIO_EN2 Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 EN2_SET GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. 0x78 ALL Mask of all of the pins on the port. 0 32 EN2_CLR GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. 0x7C ALL Mask of all of the pins on the port. 0 32 HYSEN GPIO Input Hysteresis Enable. 0xA8 GPIO_HYSEN Mask of all of the pins on the port. 0 32 SRSEL GPIO Slew Rate Enable Register. 0xAC GPIO_SRSEL Mask of all of the pins on the port. 0 32 FAST Fast Slew Rate selected. 0 SLOW Slow Slew Rate selected. 1 DS0 GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. 0xB0 GPIO_DS0 Mask of all of the pins on the port. 0 32 ld GPIO port pin is in low-drive mode. 0 hd GPIO port pin is in high-drive mode. 1 DS1 GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. 0xB4 GPIO_DS1 Mask of all of the pins on the port. 0 32 PS GPIO Pull Select Mode. 0xB8 ALL Mask of all of the pins on the port. 0 32 VSSEL GPIO Voltage Select. 0xC0 ALL Mask of all of the pins on the port. 0 32 GPIO1 Individual I/O for each GPIO 1 0x40009000 GPIO1 GPIO1 IRQ 25 I2C0 Inter-Integrated Circuit. I2C 0x4001D000 32 0x00 0x1000 registers I2C0 I2C0 IRQ 13 CTRL Control Register0. 0x00 EN I2C Enable. [0:0] read-write dis Disable I2C. 0 en enable I2C. 1 MST_MODE Master Mode Enable. [1:1] read-write slave_mode Slave Mode. 0 master_mode Master Mode. 1 GC_ADDR_EN General Call Address Enable. [2:2] read-write dis Ignore Gneral Call Address. 0 en Acknowledge general call address. 1 IRXM_EN Interactive Receive Mode. [3:3] read-write dis Disable Interactive Receive Mode. 0 en Enable Interactive Receive Mode. 1 IRXM_ACK Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. [4:4] read-write ack return ACK (pulling SDA LOW). 0 nack return NACK (leaving SDA HIGH). 1 SCL_OUT SCL Output. This bits control SCL output when SWOE =1. [6:6] read-write drive_scl_low Drive SCL low. 0 release_scl Release SCL. 1 SDA_OUT SDA Output. This bits control SDA output when SWOE = 1. [7:7] read-write drive_sda_low Drive SDA low. 0 release_sda Release SDA. 1 SCL SCL status. This bit reflects the logic gate of SCL signal. [8:8] read-only SDA SDA status. THis bit reflects the logic gate of SDA signal. [9:9] read-only BB_MODE Software Output Enable. [10:10] read-write outputs_disable I2C Outputs SCLO and SDAO disabled. 0 outputs_enable I2C Outputs SCLO and SDAO enabled. 1 READ Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. [11:11] read-only write Write. 0 read Read. 1 CLKSTR_DIS This bit will disable slave clock stretching when set. [12:12] read-write en Slave clock stretching enabled. 0 dis Slave clock stretching disabled. 1 ONE_MST_MODE SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. [13:13] read-write dis Standard open-drain operation: drive low for 0, Hi-Z for 1 0 en Non-standard push-pull operation: drive low for 0, drive high for 1 1 HS_EN High speed mode enable [15:15] read-write STATUS Status Register. 0x04 BUSY Bus Status. [0:0] read-only idle I2C Bus Idle. 0 busy I2C Bus Busy. 1 RX_EM RX empty. [1:1] read-only not_empty Not Empty. 0 empty Empty. 1 RX_FULL RX Full. [2:2] read-only not_full Not Full. 0 full Full. 1 TX_EM TX Empty. [3:3] not_empty Not Empty. 0 empty Empty. 1 TX_FULL TX Full. [4:4] not_empty Not Empty. 0 empty Empty. 1 MST_BUSY Clock Mode. [5:5] read-only not_actively_driving_scl_clock Device not actively driving SCL clock cycles. 0 actively_driving_scl_clock Device operating as master and actively driving SCL clock cycles. 1 INTFL0 Interrupt Status Register. 0x08 DONE Transfer Done Interrupt. [0:0] INT_FL0_Done inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 IRXM Interactive Receive Interrupt. [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 GC_ADDR_MATCH Slave General Call Address Match Interrupt. [2:2] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADDR_MATCH Slave Address Match Interrupt. [3:3] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 RX_THD Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. [4:4] inactive No interrupt is pending. 0 pending An interrupt is pending. RX_FIFO equal or more bytes than the threshold. 1 TX_THD Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. [5:5] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 STOP STOP Interrupt. [6:6] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 ADDR_ACK Address Acknowledge Interrupt. [7:7] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ARB_ERR Arbritation error Interrupt. [8:8] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TO_ERR timeout Error Interrupt. [9:9] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADDR_NACK_ERR Address NACK Error Interrupt. [10:10] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DATA_ERR Data NACK Error Interrupt. [11:11] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DNR_ERR Do Not Respond Error Interrupt. [12:12] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 START_ERR Start Error Interrupt. [13:13] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 STOP_ERR Stop Error Interrupt. [14:14] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TX_LOCKOUT Transmit Lock Out Interrupt. [15:15] MAMI Multiple Address Match Interrupt [21:16] RD_ADDR_MATCH Slave Read Address Match Interrupt [22:22] WR_ADDR_MATCH Slave Write Address Match Interrupt [23:23] INTEN0 Interrupt Enable Register. 0x0C read-write DONE Transfer Done Interrupt Enable. [0:0] read-write dis Interrupt disabled. 0 en Interrupt enabled when DONE = 1. 1 IRXM Description not available. [1:1] read-write dis Interrupt disabled. 0 en Interrupt enabled when RX_MODE = 1. 1 GC_ADDR_MATCH Slave mode general call address match received input enable. [2:2] read-write dis Interrupt disabled. 0 en Interrupt enabled when GEN_CTRL_ADDR = 1. 1 ADDR_MATCH Slave mode incoming address match interrupt. [3:3] read-write dis Interrupt disabled. 0 en Interrupt enabled when ADDR_MATCH = 1. 1 RX_THD RX FIFO Above Treshold Level Interrupt Enable. [4:4] read-write dis Interrupt disabled. 0 en Interrupt enabled. 1 TX_THD TX FIFO Below Treshold Level Interrupt Enable. [5:5] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOP Stop Interrupt Enable [6:6] read-write dis Interrupt disabled. 0 en Interrupt enabled when STOP = 1. 1 ADDR_ACK Received Address ACK from Slave Interrupt. [7:7] dis Interrupt disabled. 0 en Interrupt enabled. 1 ARB_ERR Master Mode Arbitration Lost Interrupt. [8:8] dis Interrupt disabled. 0 en Interrupt enabled. 1 TO_ERR Timeout Error Interrupt Enable. [9:9] dis Interrupt disabled. 0 en Interrupt enabled. 1 ADDR_NACK_ERR Master Mode Address NACK Received Interrupt. [10:10] dis Interrupt disabled. 0 en Interrupt enabled. 1 DATA_ERR Master Mode Data NACK Received Interrupt. [11:11] dis Interrupt disabled. 0 en Interrupt enabled. 1 DNR_ERR Slave Mode Do Not Respond Interrupt. [12:12] dis Interrupt disabled. 0 en Interrupt enabled. 1 START_ERR Out of Sequence START condition detected interrupt. [13:13] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOP_ERR Out of Sequence STOP condition detected interrupt. [14:14] dis Interrupt disabled. 0 en Interrupt enabled. 1 TX_LOCKOUT TX FIFO Locked Out Interrupt. [15:15] MAMI Multiple Address Match Interrupt [21:16] RD_ADDR_MATCH Slave Read Address Match Interrupt [22:22] WR_ADDR_MATCH Slave Write Address Match Interrupt [23:23] INTFL1 Interrupt Status Register 1. 0x10 RX_OV Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. [0:0] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TX_UN Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 START START Condition Status Flag. [2:2] INTEN1 Interrupt Staus Register 1. 0x14 read-write RX_OV Receiver Overflow Interrupt Enable. [0:0] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 TX_UN Transmit Underflow Interrupt Enable. [1:1] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 START START Condition Interrupt Enable. [2:2] FIFOLEN FIFO Configuration Register. 0x18 RX_DEPTH Receive FIFO Length. [7:0] read-only TX_DEPTH Transmit FIFO Length. [15:8] read-only RXCTRL0 Receive Control Register 0. 0x1C DNR Do Not Respond. [0:0] respond Always respond to address match. 0 not_respond_rx_fifo_empty Do not respond to address match when RX_FIFO is not empty. 1 FLUSH Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. [7:7] not_flushed FIFO not flushed. 0 flush Flush RX_FIFO. 1 THD_LVL Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. [11:8] RXCTRL1 Receive Control Register 1. 0x20 CNT Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. [7:0] LVL Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. [11:8] read-only TXCTRL0 Transmit Control Register 0. 0x24 PRELOAD_MODE Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. [0:0] TX_READY_MODE Transmit FIFO Ready Manual Mode. [1:1] en HW control of I2CTXRDY enabled. 0 dis HW control of I2CTXRDY disabled. 1 GC_ADDR_FLUSH_DIS TX FIFO General Call Address Match Auto Flush Disable. [2:2] en Enabled. 0 dis Disabled. 1 WR_ADDR_FLUSH_DIS TX FIFO Slave Address Match Write Auto Flush Disable. [3:3] en Enabled. 0 dis Disabled. 1 RD_ADDR_FLUSH_DIS TX FIFO Slave Address Match Read Auto Flush Disable. [4:4] en Enabled. 0 dis Disabled. 1 NACK_FLUSH_DIS TX FIFO received NACK Auto Flush Disable. [5:5] en Enabled. 0 dis Disabled. 1 FLUSH Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. [7:7] not_flushed FIFO not flushed. 0 flush Flush TX_FIFO. 1 THD_LVL Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. [11:8] TXCTRL1 Transmit Control Register 1. 0x28 PRELOAD_RDY Transmit FIFO Preload Ready. [0:0] LVL Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. [11:8] read-only FIFO Data Register. 0x2C DATA Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. 0 8 MSTCTRL Master Control Register. 0x30 START Setting this bit to 1 will start a master transfer. [0:0] RESTART Setting this bit to 1 will generate a repeated START. [1:1] STOP Setting this bit to 1 will generate a STOP condition. [2:2] EX_ADDR_EN Slave Extend Address Select. [7:7] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 CLKLO Clock Low Register. 0x34 LO Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. [8:0] CLKHI Clock high Register. 0x38 HI Clock High. In master mode, these bits define the SCL high period. [8:0] HSCLK Clock high Register. 0x3C LO Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. [7:0] HI Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA [15:8] TIMEOUT Timeout Register 0x40 SCL_TO_VAL Timeout [15:0] DMA DMA Register. 0x48 TX_EN TX channel enable. [0:0] dis Disable. 0 en Enable. 1 RX_EN RX channel enable. [1:1] dis Disable. 0 en Enable. 1 4 4 SLAVE_MULTI[%s] Slave Address Register. SLAVE0 0x4C 32 read-write ADDR Slave Address. [9:0] DIS Slave Disable. [10:10] EXT_ADDR_EN Extended Address Select. [15:15] 7_bits_address 7-bit address. 0 10_bits_address 10-bit address. 1 SLAVE0 Slave Address Register. 0x4C SLAVE1 Slave Address Register. 0x50 SLAVE2 Slave Address Register. 0x54 SLAVE3 Slave Address Register. 0x58 I2C1 Inter-Integrated Circuit. 1 0x4001E000 I2C1 I2C1 IRQ 36 I2C2 Inter-Integrated Circuit. 2 0x4001F000 I2C2 I2C2 IRQ 62 I2S Inter-IC Sound Interface. I2S 0x40060000 32 0x00 0x1000 registers I2S I2S IRQ 99 CTRL0CH0 Global mode channel. 0x00 LSB_FIRST LSB Transmit Receive First. [1:1] read-write PDM_FILT PDM Filter. [2:2] read-write PDM_EN PDM Enable. [3:3] read-write USEDDR DDR. [4:4] read-write PDM_INV Invert PDM. [5:5] read-write CH_MODE SCK Select. [7:6] read-write WS_POL WS polarity select. [8:8] read-write MSB_LOC MSB location. [9:9] read-only ALIGN Align to MSB or LSB. [10:10] read-only EXT_SEL External SCK/WS selection. [11:11] read-write STEREO Stereo mode of I2S. [13:12] read-only WSIZE Data size when write to FIFO. [15:14] read-write TX_EN TX channel enable. [16:16] read-write RX_EN RX channel enable. [17:17] read-write FLUSH Flushes the TX/RX FIFO buffer. [18:18] read-write RST Write 1 to reset channel. [19:19] read-write FIFO_LSB Bit Field Control. [20:20] read-write RX_THD_VAL depth of receive FIFO for threshold interrupt generation. [31:24] read-write CTRL1CH0 Local channel Setup. 0x10 BITS_WORD I2S word length. [4:0] read-write EN I2S clock enable. [8:8] read-write SMP_SIZE I2S sample size length. [13:9] read-write ADJUST LSB/MSB Justify. [15:15] read-write CLKDIV I2S clock frequency divisor. [31:16] read-write FILTCH0 Filter. 0x20 DMACH0 DMA Control. 0x30 DMA_TX_THD_VAL TX FIFO Level DMA Trigger. [6:0] read-write DMA_TX_EN TX DMA channel enable. [7:7] read-write DMA_RX_THD_VAL RX FIFO Level DMA Trigger. [14:8] read-write DMA_RX_EN RX DMA channel enable. [15:15] read-write TX_LVL Number of data word in the TX FIFO. [23:16] read-write RX_LVL Number of data word in the RX FIFO. [31:24] read-write FIFOCH0 I2S Fifo. 0x40 DATA Load/unload location for TX and RX FIFO buffers. [31:0] read-write INTFL ISR Status. 0x50 RX_OV_CH0 Status for RX FIFO Overrun interrupt. [0:0] read-write RX_THD_CH0 Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. [1:1] read-write TX_OB_CH0 Status for interrupt when TX FIFO has only one byte remaining. [2:2] read-write TX_HE_CH0 Status for interrupt when TX FIFO is half empty. [3:3] read-write INTEN Interrupt Enable. 0x54 RX_OV_CH0 Enable for RX FIFO Overrun interrupt. [0:0] read-write RX_THD_CH0 Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. [1:1] read-write TX_OB_CH0 Enable for interrupt when TX FIFO has only one byte remaining. [2:2] read-write TX_HE_CH0 Enable for interrupt when TX FIFO is half empty. [3:3] read-write EXTSETUP Ext Control. 0x58 EXT_BITS_WORD Word Length for ch_mode. [4:0] read-write WKEN Wakeup Enable. 0x5C WKFL Wakeup Flags. 0x60 ICC0 Instruction Cache Controller Registers 0x4002A000 0x00 0x800 registers INFO Cache ID Register. 0x0000 read-only RELNUM Release Number. Identifies the RTL release version. 0 6 PARTNUM Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. 6 4 ID Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. 10 6 SZ Memory Configuration Register. 0x0004 read-only 0x00080008 CCH Cache Size. Indicates total size in Kbytes of cache. 0 16 MEM Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. 16 16 CTRL Cache Control and Status Register. 0x0100 EN Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. 0 1 dis Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. 0 en Cache Enabled. 1 RDY Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. 16 1 read-only notReady Not Ready. 0 ready Ready. 1 INVALIDATE Invalidate All Registers. 0x0700 read-write INVALID Invalidate. 0 32 MCR Misc Control. 0x40106C00 0x00 0x400 registers RST Low Power Reset Control Register 0x04 LPTMR0 Low Power Timer0 Reset. 0 1 reset read-write reset_done Reset complete. 0 busy Starts Reset or indicates reset in progress. 1 LPTMR1 Low Power Timer1 Reset. 1 1 LPUART0 Low Power UART0 Reset. 2 1 RTC RTC Reset. 3 1 CLKCTRL Clock Control. 0x08 ERTCO_PD 32KHz Crystal Oscillator Power Down. 16 1 ERTCO_EN 32KHz Crystal Oscillator Enable. 17 1 dis Is Disabled. 0 en Is Enabled. 1 AINCOMP AIN Comparator. 0x0C PD AIN Comparator Power Down control. 0 2 HYST AIN Comparator Hysteresis control. 2 2 NSEL_COMP0 Negative input select for AIN Comparator 0. 16 4 PSEL_COMP0 Positive input select for AIN Comparator 0 20 4 NSEL_COMP1 Negative input select for AIN Comparator 1 24 4 PSEL_COMP1 Positive input select for AIN Comparator 1 28 4 LPPIOCTRL Low Power Peripheral IO Control Register. 0x10 LPTMR0_I Enable control for LPTMR0 input. 0 1 LPTMR0_O Enable control for LPTMR0 output. 1 1 LPTMR1_I Enable control for LPTMR1 input. 2 1 LPTMR1_O Enable control for LPTMR1 output. 3 1 LPUART0_RX Enable control for LPUART0 RX. 4 1 LPUART0_TX Enable control for LPUART0 TX. 5 1 LPUART0_CTS Enable control for LPUART0 CTS. 6 1 LPUART0_RTS Enable control for LPUART0 RTS. 7 1 PCLKDIS Low Power Peripheral Clock Disable. 0x24 LPTMR0 Low Power Timer0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 LPTMR1 Low Power Timer1 Clock Disable. 1 1 LPUART0 Low Power UART0 Clock Disable. 2 1 AESKEY AES Key Pointer and Status. 0x34 PTR AESKEY Pointer and Status. 0 16 ADC_CFG0 ADC Cfig Register0. 0x38 LP_5K_DIS Disable 5K divider option in low power modes 0 1 en Enable. 0 dis Disable. 1 LP_50K_DIS Disable 50K divider option in low power modes 1 1 EN Enable. 0 DIS Disable. 1 EXT_REF External Reference 2 1 REF_SEL Reference Select 3 1 ADC_CFG1 ADC Config Register1. 0x3C CH0_PU_DYN ADC PU Dynamic Control for CH0 0 1 dis divider select always used. 0 en divider select only used when channel is selected. 1 CH1_PU_DYN ADC PU Dynamic Control for CH1 1 1 CH2_PU_DYN ADC PU Dynamic Control for CH2 2 1 CH3_PU_DYN ADC PU Dynamic Control for CH3 3 1 CH4_PU_DYN ADC PU Dynamic Control for CH4 4 1 CH5_PU_DYN ADC PU Dynamic Control for CH5 5 1 CH6_PU_DYN ADC PU Dynamic Control for CH6 6 1 CH7_PU_DYN ADC PU Dynamic Control for CH7 7 1 CH8_PU_DYN ADC PU Dynamic Control for CH8 8 1 CH9_PU_DYN ADC PU Dynamic Control for CH9 9 1 CH10_PU_DYN ADC PU Dynamic Control for CH10 10 1 CH11_PU_DYN ADC PU Dynamic Control for CH11 11 1 CH12_PU_DYN ADC PU Dynamic Control for CH12 12 1 ADC_CFG2 ADC Config Register2. 0x40 CH0 Divider Select for channel 0 0 2 div1 Pass through, no divider. 0 div2_5k Divide by 2, 5Kohm. 1 div2_50k Divide by 2, 50Kohm. 2 CH1 Divider Select for channel 1 2 2 CH2 Divider Select for channel 2 4 2 CH3 Divider Select for channel 3 6 2 CH4 Divider Select for channel 4 8 2 CH5 Divider Select for channel 5 10 2 CH6 Divider Select for channel 6 12 2 CH7 Divider Select for channel 7 14 2 CH8 Divider Select for channel 8 16 2 CH9 Divider Select for channel 9 18 2 CH10 Divider Select for channel 10 20 2 CH11 Divider Select for channel 11 22 2 CH12 Divider Select for channel 12 24 2 ADC_CFG3 ADC Config Register3. 0x44 VREFM VREFM 0 7 VREFP VREFP 8 7 IDRV IDRV 16 4 VCM VCM 20 2 ATB ATB 22 2 D_IBOOST D_IBOOST 24 1 PWRSEQ Power Sequencer / Low Power Control Register. 0x40106800 0x00 0x400 registers LPCN Low Power Control Register. 0x00 RAM0RET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 1 read-write dis Disable Ram Retention. 0 en Enable System RAM 0 retention. 1 RAM1RET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 1 1 read-write dis Disable Ram Retention. 0 en Enable System RAM 1 retention. 1 RAM2RET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 2 1 read-write dis Disable Ram Retention. 0 en Enable System RAM 2 retention. 1 RAM3RET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 3 1 read-write dis Disable Ram Retention. 0 en Enable System RAM 3 retention. 1 OVR Operating Voltage Range 4 2 read-write 0_9V 0.9V 12MHz 0 1_0V 1.0V 48MHz 1 1_1V 1.1V 96MHz 2 VCORE_DET_BYPASS Block Auto-Detect 6 1 read-write en enable 0 dis disable 1 FVDDEN Flash VDD Enable, force the flash VDD to remain enabled during LP modes. 7 1 read-write dis enable 0 en disable 1 RETREG_EN Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. 8 1 read-write dis Disabled. 0 en Enabled. 1 STORAGE_EN STORAGE Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep. 9 1 read-write dis Disabled. 0 en Enabled. 1 FASTWK_EN Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). 10 1 read-write dis Disabled. 0 en Enabled. 1 BG_DIS Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 read-write on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode (default). 1 VCOREPOR_DIS VDDC (Vcore) Power on reset Monitor Disable.This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. 12 1 read-write en Enable 0 dis Disabled. 1 LDO_DIS Disable Main LDO 16 1 read-write en Enable 0 dis Disabled. 1 VCORE_EXT Use external VCORE for 1V supply 17 1 read-write dis disable 0 en use Vcore for retention. 1 VCOREMON_DIS VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. 20 1 read-write en Enable 0 dis Disabled. 1 VDDAMON_DIS VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 22 1 read-write en Enable if Bandgap is ON (default) 0 dis Disabled. 1 PORVDDMON_DIS VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. 25 1 read-write dis Disabled. 0 en Enabled. 1 VBBMON_DIS VBB Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 27 1 read-write en Enable if Bandgap is ON (default) 0 dis Disabled. 1 INRO_EN INRO remains on in all power modes if this bit is set otherwise it is controled by the LP controller 28 1 read-write ERTCO_EN XRTCO remains on in all power modes if this bit is set otherwise it is controled by the LP controller 29 1 read-write TM_LPMODE TBD 30 1 read-write TM_PWRSEQ TBD 31 1 read-write LPWKST0 Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 ST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 31 read-write oneToClear LPWKEN0 Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 EN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 31 read-write LPWKST1 Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C LPWKEN1 Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 LPPWKST Low Power Peripheral Wakeup Status Register. 0x30 LPTMR0 LPTM0 Wakeup Flag. 0 1 read-write oneToClear LPTMR1 LPTMR1 Wakeup Flag. 1 1 read-write oneToClear LPUART0 LPUART0 Wakeup Flag. 2 1 read-write oneToClear AINCOMP0 AINCOMP0 Wakeup Flag. 3 1 read-write oneToClear AINCOMP1 AINCOMP1 Wakeup Flag. 4 1 read-write oneToClear AINCOMP0_OUT AINCOMP0 Status. 5 1 read-only AINCOMP1_OUT AINCOMP1 Status. 6 1 read-only BACKUP BBMODE Wakeup Flag. 16 1 read-write oneToClear LPPWKEN Low Power Peripheral Wakeup Enable Register. 0x34 LPTMR0 TIMER4 Wakeup Enable. This bit allows wakeup from the TIMER4. 0 1 read-write LPTMR1 TIMER5 Wakeup Enable. This bit allows wakeup from the TIMER5. 1 1 read-write LPUART0 LPUART Wakeup Enable. This bit allows wakeup from the LPUART. 2 1 read-write AINCOMP0 AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. 3 1 read-write AINCOMP1 AINCOMP1 Wakeup Enable. This bit allows wakeup from the AINCOMP1. 4 1 read-write LPMEMSD Low Power Memory Shutdown Control. 0x40 RAM0 System RAM block 0 Shut Down. 0 1 read-write normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM1 System RAM block 1 Shut Down. 1 1 read-write normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM2 System RAM block 2 Shut Down. 2 1 read-write normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RAM3 System RAM block 3 Shut Down. 3 1 read-write normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 GPR0 General Purpose Register 0. 0x48 GPR1 General Purpose Register 1. 0x4C QDEC Quadrature Encoder Interface 0x40063000 0x00 0x1000 registers CTRL Control Register. 0x0000 en 0 1 read-write enum disable 0x0 enable 0x1 mode 1 2 read-write enum x1mode 0 x2mode 1 x4mode 2 swap 3 1 read-write filter 4 2 read-write enum 1_sample 0 2_samples 1 3_samples 2 4_samples 3 rst_index 6 1 read-write rst_maxcnt 7 1 read-write sticky 8 1 read-write psc 16 3 read-write enum div1 0 div2 1 div4 2 div8 3 div16 4 div32 5 div64 6 div128 7 INTFL Interrupt Flag Register. 0x0004 index 0 1 read-write oneToClear qerr 1 1 read-write oneToClear compare 2 1 read-write oneToClear maxcnt 3 1 read-write oneToClear capture 4 1 read-write oneToClear dir 5 1 read-write oneToClear move 6 1 read-write oneToClear INTEN Interrupt Enable Register. 0x0008 index 0 1 read-write qerr 1 1 read-write compare 2 1 read-write maxcnt 3 1 read-write capture 4 1 read-write dir 5 1 read-write move 6 1 read-write MAXCNT Maximum Count Register. 0x000C maxcnt 0 32 read-write INITIAL Initial Count Register. 0x0010 initial 0 32 read-write COMPARE Compare Register. 0x0014 compare 0 32 read-write INDEX Index Register. count captured when QEI fired 0x0018 read-only index 0 32 read-only CAPTURE Capture Register. counter captured when QES fired 0x001C read-only capture 0 32 read-only STATUS Status Register. 0x0020 read-only dir 0 1 read-only POSITION Count Register. raw counter value 0x0024 position 0 32 read-only CAPDLY delay CAPTURE 0x0028 capdly 0 32 read-write RTC Real Time Clock and Alarm. 0x40106000 0x00 0x400 registers RTC RTC interrupt. 3 SEC RTC Second Counter. This register contains the 32-bit second counter. 0x00 0x00000000 SEC Seconds Counter. 0 32 SSEC RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 SSEC Sub-Seconds Counter (12-bit). 0 12 TODA Time-of-day Alarm. 0x08 0x00000000 TOD_ALARM Time-of-day Alarm. 0 20 SSECA RTC sub-second alarm. This register contains the reload value for the sub-second alarm. 0x0C 0x00000000 SSEC_ALARM This register contains the reload value for the sub-second alarm. 0 32 CTRL RTC Control Register. 0x10 0x00000008 0xFFFFFF38 EN Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 TOD_ALARM_IE Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 SSEC_ALARM_IE Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 RDY RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 4 1 busy Register has not updated. 0 ready Ready. 1 RDY_IE RTC Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 TOD_ALARM Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active 0 Pending Active 1 SSEC_ALARM Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active 0 Pending Active 1 SQW_EN Square Wave Output Enable. 8 1 inactive Not active 0 Pending Active 1 SQW_SEL Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 9 2 freq1Hz 1 Hz (Compensated). 0 freq512Hz 512 Hz (Compensated). 1 freq4KHz 4 KHz. 2 clkDiv8 RTC Input Clock / 8. 3 RD_EN Asynchronous Counter Read Enable. 14 1 WR_EN Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 15 1 inactive Not active 0 Pending Active 1 TRIM RTC Trim Register. 0x14 0x00000000 TRIM RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. 0 8 VRTC_TMR VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. 8 24 OSCCTRL RTC Oscillator Control Register. 0x18 0x00000000 FILTER_EN Enables analog deglitch filter. 0 1 IBIAS_SEL If IBIAS_EN is 1, selects 4x,2x mode. 1 1 HYST_EN Enables high current hysteresis buffer. 2 1 IBIAS_EN Enables higher 4x,2x current modes. 3 1 BYPASS RTC Crystal Bypass 4 1 SQW_32K RTC 32kHz Square Wave Output 5 1 SIR System Initialization Registers. 0x40000400 read-only 0x00 0x400 registers STATUS System Initialization Status Register. 0x00 read-only CFG_VALID Configuration Valid Flag. 0 1 read-only CFG_ERR Configuration Error Flag. 1 1 read-only USER_CFG_ERR User Configuration Error Flag. 2 1 read-only ADDR Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x04 read-only ADDR 0 32 FSTAT Function Status Register. 0x100 read-only FPU FPU Function. 0 1 TRNG TRNG Function. 14 1 DS_ACK DeepSleep Acknowledge. 15 1 SFSTAT Security Function Status Register. 0x104 read-only SECFUNC0 Secure Function 0 Status. 0 1 SPI0 SPI peripheral. 0x40046000 0x00 0x1000 registers SPI0 16 FIFO32 Register for reading and writing the FIFO. 0x00 32 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 32 2 2 FIFO16[%s] Register for reading and writing the FIFO. 0x00 16 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 16 4 1 FIFO8[%s] Register for reading and writing the FIFO. 0x00 8 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 8 CTRL0 Register for controlling SPI peripheral. 0x04 read-write EN SPI Enable. 0 1 dis SPI is disabled. 0 en SPI is enabled. 1 MST_MODE Master Mode Enable. 1 1 dis SPI is Slave mode. 0 en SPI is Master mode. 1 SS_IO Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 4 1 output Slave select 0 is output. 0 input Slave Select 0 is input, only valid if MMEN=1. 1 START Start Transmit. 5 1 start Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. 1 SS_CTRL Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. 8 1 DEASSERT SPI De-asserts Slave Select at the end of a transaction. 0 ASSERT SPI leaves Slave Select asserted at the end of a transaction. 1 SS_ACTIVE Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 16 4 SS0 SS0 is selected. 0x1 SS1 SS1 is selected. 0x2 SS2 SS2 is selected. 0x4 SS3 SS3 is selected. 0x8 CTRL1 Register for controlling SPI peripheral. 0x08 read-write TX_NUM_CHAR Nubmer of Characters to transmit. 0 16 RX_NUM_CHAR Nubmer of Characters to receive. 16 16 CTRL2 Register for controlling SPI peripheral. 0x0C read-write CLKPHA Clock Phase. 0 1 Rising_Edge Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 0 Falling_Edge Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 1 CLKPOL Clock Polarity. 1 1 Normal Normal Clock. Use when in SPI Mode 0 and Mode 1 0 Inverted Inverted Clock. Use when in SPI Mode 2 and Mode 3 1 SCLK_FB_INV SCLK_FB_INV. 4 1 NUMBITS Number of Bits per character. 8 4 0 16 bits per character. 0 DATA_WIDTH SPI Data width. 12 2 Mono 1 data pin. 0 Dual 2 data pins. 1 Quad 4 data pins. 2 THREE_WIRE Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 15 1 dis Use four wire mode (Mono only). 0 en Use three wire mode. 1 SS_POL Slave Select Polarity, each Slave Select can have unique polarity. 16 8 SS0_high SS0 active high. 0x1 SS1_high SS1 active high. 0x2 SS2_high SS2 active high. 0x4 SS3_high SS3 active high. 0x8 SSTIME Register for controlling SPI peripheral/Slave Select Timing. 0x10 read-write PRE Slave Select Pre delay 1. 0 8 256 256 system clocks between SS active and first serial clock edge. 0 POST Slave Select Post delay 2. 8 8 256 256 system clocks between last serial clock edge and SS inactive. 0 INACT Slave Select Inactive delay. 16 8 256 256 system clocks between transactions. 0 CLKCTRL Register for controlling SPI clock rate. 0x14 read-write LO Low duty cycle control. In timer mode, reload[7:0]. 0 8 Dis Duty cycle control of serial clock generation is disabled. 0 HI High duty cycle control. In timer mode, reload[15:8]. 8 8 Dis Duty cycle control of serial clock generation is disabled. 0 CLKDIV System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. 16 4 DMA Register for controlling DMA. 0x1C read-write TX_THD_VAL Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. 0 5 TX_FIFO_EN Transmit FIFO enabled for SPI transactions. 6 1 dis Transmit FIFO is not enabled. 0 en Transmit FIFO is enabled. 1 TX_FLUSH Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 7 1 CLEAR Clear the Transmit FIFO, clears any pending TX FIFO status. 1 TX_LVL Count of entries in TX FIFO. 8 6 read-only DMA_TX_EN TX DMA Enable. 15 1 DIS TX DMA requests are disabled, andy pending DMA requests are cleared. 0 en TX DMA requests are enabled. 1 RX_THD_VAL Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. 16 5 RX_FIFO_EN Receive FIFO enabled for SPI transactions. 22 1 DIS Receive FIFO is not enabled. 0 en Receive FIFO is enabled. 1 RX_FLUSH Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 23 1 CLEAR Clear the Receive FIFO, clears any pending RX FIFO status. 1 RX_LVL Count of entries in RX FIFO. 24 6 read-only DMA_RX_EN RX DMA Enable. 31 1 dis RX DMA requests are disabled, any pending DMA requests are cleared. 0 en RX DMA requests are enabled. 1 INTFL Register for reading and clearing interrupt flags. All bits are write 1 to clear. 0x20 read-write TX_THD TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL RX FIFO FULL. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSA Slave Select Asserted. 4 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSD Slave Select Deasserted. 5 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 FAULT Multi-Master Mode Fault. 8 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 ABORT Slave Abort Detected. 9 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 MST_DONE Master Done, set when SPI Master has completed any transactions. 11 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_OV Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 12 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_UN Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. 13 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_OV Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. 14 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_UN Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. 15 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 INTEN Register for enabling interrupts. 0x24 read-write TX_THD TX FIFO Threshold interrupt enable. 0 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_EM TX FIFO Empty interrupt enable. 1 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_THD RX FIFO Threshold Crossed interrupt enable. 2 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_FULL RX FIFO FULL interrupt enable. 3 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSA Slave Select Asserted interrupt enable. 4 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSD Slave Select Deasserted interrupt enable. 5 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 FAULT Multi-Master Mode Fault interrupt enable. 8 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 ABORT Slave Abort Detected interrupt enable. 9 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 MST_DONE Master Done interrupt enable. 11 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_OV Transmit FIFO Overrun interrupt enable. 12 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_UN Transmit FIFO Underrun interrupt enable. 13 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_OV Receive FIFO Overrun interrupt enable. 14 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_UN Receive FIFO Underrun interrupt enable. 15 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 WKFL Register for wake up flags. All bits in this register are write 1 to clear. 0x28 read-write TX_THD Wake on TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EM Wake on TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_THD Wake on RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL Wake on RX FIFO Full. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 WKEN Register for wake up enable. 0x2C read-write TX_THD Wake on TX FIFO Threshold Crossed Enable. 0 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 TX_EM Wake on TX FIFO Empty Enable. 1 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_THD Wake on RX FIFO Threshold Crossed Enable. 2 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_FULL Wake on RX FIFO Full Enable. 3 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 STAT SPI Status register. 0x30 read-only BUSY SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 0 1 not SPI not active. 0 active SPI active. 1 SPI1 SPI peripheral. 1 0x40047000 SPI1 SPI1 IRQ 17 SPI2 SPI peripheral. 2 0x40048000 SPI2 SPI2 IRQ 18 TMR Low-Power Configurable Timer 0x40010000 0x00 0x1000 registers TMR 5 CNT Timer Counter Register. 0x00 read-write COUNT The current count value for the timer. This field increments as the timer counts. 0 32 CMP Timer Compare Register. 0x04 read-write COMPARE The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. 0 32 PWM Timer PWM Register. 0x08 read-write PWM Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. 0 32 INTFL Timer Interrupt Status Register. 0x0C read-write IRQ_A Interrupt Flag for Timer A. 0 1 WRDONE_A Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. 8 1 WR_DIS_A Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. 9 1 IRQ_B Interrupt Flag for Timer B. 16 1 WRDONE_B Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. 24 1 WR_DIS_B Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. 25 1 CTRL0 Timer Control Register. 0x10 read-write MODE_A Mode Select for Timer A 0 4 ONE_SHOT One-Shot Mode 0 CONTINUOUS Continuous Mode 1 COUNTER Counter Mode 2 PWM PWM Mode 3 CAPTURE Capture Mode 4 COMPARE Compare Mode 5 GATED Gated Mode 6 CAPCOMP Capture/Compare Mode 7 DUAL_EDGE Dual Edge Capture Mode 8 IGATED Inactive Gated Mode 12 CLKDIV_A Clock Divider Select for Timer A 4 4 DIV_BY_1 Prescaler Divide-By-1 0 DIV_BY_2 Prescaler Divide-By-2 1 DIV_BY_4 Prescaler Divide-By-4 2 DIV_BY_8 Prescaler Divide-By-8 3 DIV_BY_16 Prescaler Divide-By-16 4 DIV_BY_32 Prescaler Divide-By-32 5 DIV_BY_64 Prescaler Divide-By-64 6 DIV_BY_128 Prescaler Divide-By-128 7 DIV_BY_256 Prescaler Divide-By-256 8 DIV_BY_512 Prescaler Divide-By-512 9 DIV_BY_1024 Prescaler Divide-By-1024 10 DIV_BY_2048 Prescaler Divide-By-2048 11 DIV_BY_4096 TBD 12 POL_A Timer Polarity for Timer A 8 1 PWMSYNC_A PWM Synchronization Mode for Timer A 9 1 NOLHPOL_A PWM Phase A (Non-Overlapping High) Polarity for Timer A 10 1 NOLLPOL_A PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A 11 1 PWMCKBD_A PWM Phase A-Prime Output Disable for Timer A 12 1 RST_A Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. 13 1 CLKEN_A Write 1 to Enable CLK_TMR for Timer A 14 1 EN_A Enable for Timer A 15 1 MODE_B Mode Select for Timer B 16 4 ONE_SHOT One-Shot Mode 0 CONTINUOUS Continuous Mode 1 COUNTER Counter Mode 2 PWM PWM Mode 3 CAPTURE Capture Mode 4 COMPARE Compare Mode 5 GATED Gated Mode 6 CAPCOMP Capture/Compare Mode 7 DUAL_EDGE Dual Edge Capture Mode 8 IGATED Inactive Gated Mode 14 CLKDIV_B Clock Divider Select for Timer B 20 4 DIV_BY_1 Prescaler Divide-By-1 0 DIV_BY_2 Prescaler Divide-By-2 1 DIV_BY_4 Prescaler Divide-By-4 2 DIV_BY_8 Prescaler Divide-By-8 3 DIV_BY_16 Prescaler Divide-By-16 4 DIV_BY_32 Prescaler Divide-By-32 5 DIV_BY_64 Prescaler Divide-By-64 6 DIV_BY_128 Prescaler Divide-By-128 7 DIV_BY_256 Prescaler Divide-By-256 8 DIV_BY_512 Prescaler Divide-By-512 9 DIV_BY_1024 Prescaler Divide-By-1024 10 DIV_BY_2048 Prescaler Divide-By-2048 11 DIV_BY_4096 TBD 12 POL_B Timer Polarity for Timer B 24 1 PWMSYNC_B PWM Synchronization Mode for Timer B 25 1 NOLHPOL_B PWM Phase A (Non-Overlapping High) Polarity for Timer B 26 1 NOLLPOL_B PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B 27 1 PWMCKBD_B PWM Phase A-Prime Output Disable for Timer B 28 1 RST_B Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. 29 1 CLKEN_B Write 1 to Enable CLK_TMR for Timer B 30 1 EN_B Enable for Timer B 31 1 NOLCMP Timer Non-Overlapping Compare Register. 0x14 read-write LO_A Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. 0 8 HI_A Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. 8 8 LO_B Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. 16 8 HI_B Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. 24 8 CTRL1 Timer Configuration Register. 0x18 read-write CLKSEL_A Timer Clock Select for Timer A 0 2 CLKEN_A Timer A Enable Status 2 1 CLKRDY_A CLK_TMR Ready Flag for Timer A 3 1 EVENT_SEL_A Event Select for Timer A 4 3 NEGTRIG_A Negative Edge Trigger for Event for Timer A 7 1 IE_A Interrupt Enable for Timer A 8 1 CAPEVENT_SEL_A Capture Event Select for Timer A 9 2 SW_CAPEVENT_A Software Capture Event for Timer A 11 1 WE_A Wake-Up Enable for Timer A 12 1 OUTEN_A OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A 13 1 OUTBEN_A PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A 14 1 CLKSEL_B Timer Clock Select for Timer B 16 2 CLKEN_B Timer B Enable Status 18 1 CLKRDY_B CLK_TMR Ready Flag for Timer B 19 1 EVENT_SEL_B Event Select for Timer B 20 3 NEGTRIG_B Negative Edge Trigger for Event for Timer B 23 1 IE_B Interrupt Enable for Timer B 24 1 CAPEVENT_SEL_B Capture Event Select for Timer B 25 2 SW_CAPEVENT_B Software Capture Event for Timer B 27 1 WE_B Wake-Up Enable for Timer B 28 1 CASCADE Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. 31 1 WKFL Timer Wakeup Status Register. 0x1C read-write A Wake-Up Flag for Timer A 0 1 B Wake-Up Flag for Timer B 16 1 TMR1 Low-Power Configurable Timer 1 0x40011000 TMR1 TMR1 IRQ 6 TMR2 Low-Power Configurable Timer 2 0x40012000 TMR2 TMR2 IRQ 7 TMR3 Low-Power Configurable Timer 3 0x40013000 TMR3 TMR3 IRQ 8 TMR4 Low-Power Configurable Timer 4 0x40114000 TMR4 TMR4 IRQ 9 TMR5 Low-Power Configurable Timer 5 0x40115000 TMR5 TMR5 IRQ 10 TRIMSIR Trim System Initilazation Registers 0x40105400 0x00 0x400 registers BB_SIR2 System Init. Configuration Register 2. 0x08 read-write TRIM_IBRO_RBIAS HIRC8M Trim 0 6 RAM0_1ECCEN RAM 0 and RAM 1 ECC Enable 8 1 dis ECC Disabled. 0 en ECC Enabled. 1 RAM2ECCEN RAM 2 ECC Enable 9 1 RAM3ECCEN RAM 3 ECC Enable 10 1 ICC0ECCEN ICC 0 ECC Enable 11 1 FL0ECCEN Flash 0 ECC Enable 12 1 FL1ECCEN Flash 1 ECC Enable 13 1 TRIM_IBRO HIRC8M Trim 16 16 BB_SIR3 System Init. Configuration Register 3. 0x0C read-write BB_SIR6 System Init. Configuration Register 6. 0x18 read-only RTCX1TRIM RTCX1 Trim 4 5 RTCX2TRIM RTCX2 Trim 9 5 TRNG Random Number Generator. 0x4004D000 0x00 0x1000 registers TRNG TRNG interrupt. 4 CTRL TRNG Control Register. 0x00 0x00000003 ODHT Start On-Demand health test. 0 1 RND_IE To enable IRQ generation when a new 32-bit Random number is ready. 1 1 disable Disable 0 enable Enable 1 HEALTH_EN Enable IRQ generation when a health test fails. 2 1 AESKG_USR AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. 3 1 AESKG_SYS AESKG_SYS. 4 1 KEYWIPE To wipe the Battery Backed key. 15 1 STATUS Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x04 RDY 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. 0 1 Busy TRNG Busy 0 Ready 32 bit random data is ready 1 ODHT On-Demand health test status. 1 1 HT Health test status. 2 1 SRCFAIL Entropy source has failed. 3 1 AESKGD AESKGD. 4 1 LD_CNT LD_CNT. 24 8 DATA Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x08 read-only DATA Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. 0 32 UART UART Low Power Registers 0x40042000 0x00 0x1000 registers CTRL Control register 0x0000 RX_THD_VAL This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) 0 4 PAR_EN Parity Enable 4 1 PAR_EO when PAREN=1 selects odd or even parity odd is 1 even is 0 5 1 PAR_MD Selects parity based on 1s or 0s count (when PAREN=1) 6 1 CTS_DIS CTS Sampling Disable 7 1 TX_FLUSH Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. 8 1 RX_FLUSH Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. 9 1 CHAR_SIZE Selects UART character size 10 2 5bits 5 bits 0 6bits 6 bits 1 7bits 7 bits 2 8bits 8 bits 3 STOPBITS Selects the number of stop bits that will be generated 12 1 HFC_EN Enables/disables hardware flow control 13 1 RTSDC Hardware Flow Control RTS Mode 14 1 BCLKEN Baud clock enable 15 1 BCLKSRC To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. 16 2 Peripheral_Clock apb clock 0 External_Clock Clock 1 1 CLK2 Clock 2 2 CLK3 Clock 3 3 DPFE_EN Data/Parity bit frame error detection enable 18 1 BCLKRDY Baud clock Ready read only bit 19 1 UCAGM UART Clock Auto Gating mode 20 1 FDM Fractional Division Mode 21 1 DESM RX Dual Edge Sampling Mode 22 1 STATUS Status register 0x0004 read-only TX_BUSY Read-only flag indicating the UART transmit status 0 1 RX_BUSY Read-only flag indicating the UART receiver status 1 1 RX_EM Read-only flag indicating the RX FIFO state 4 1 RX_FULL Read-only flag indicating the RX FIFO state 5 1 TX_EM Read-only flag indicating the TX FIFO state 6 1 TX_FULL Read-only flag indicating the TX FIFO state 7 1 RX_LVL Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) 8 4 TX_LVL Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) 12 4 INT_EN Interrupt Enable control register 0x0008 RX_FERR Enable Interrupt For RX Frame Error 0 1 RX_PAR Enable Interrupt For RX Parity Error 1 1 CTS_EV Enable Interrupt For CTS signal change Error 2 1 RX_OV Enable Interrupt For RX FIFO Overrun Error 3 1 RX_THD Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD 4 1 TX_OB Enable Interrupt For TX FIFO has one byte remaining 5 1 TX_HE Enable Interrupt For TX FIFO has half empty 6 1 INT_FL Interrupt status flags Control register 0x000C RX_FERR Flag for RX Frame Error Interrupt. 0 1 RX_PAR Flag for RX Parity Error interrupt 1 1 CTS_EV Flag for CTS signal change interrupt (hardware flow control disabled) 2 1 RX_OV Flag for RX FIFO Overrun interrupt 3 1 RX_THD Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field 4 1 TX_OB Flag for interrupt when TX FIFO has one byte remaining 5 1 TX_HE Flag for interrupt when TX FIFO is half empty 6 1 CLKDIV Clock Divider register 0x0010 CLKDIV Baud rate divisor value 0 20 OSR Over Sampling Rate register 0x0014 OSR OSR 0 3 TXPEEK TX FIFO Output Peek register 0x0018 DATA Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field. 0 8 PNR Pin register 0x001C CTS Current sampled value of CTS IO 0 1 read-only RTS This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level. 1 1 FIFO FIFO Read/Write register 0x0020 DATA Load/unload location for TX and RX FIFO buffers. 0 8 RX_PAR Parity error flag for next byte to be read from FIFO. 8 1 DMA DMA Configuration register 0x0030 TX_THD_VAL TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory. 0 4 TX_EN TX DMA channel enable 4 1 RX_THD_VAL Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory. 5 4 RX_EN RX DMA channel enable 9 1 WKEN Wake up enable Control register 0x0034 RX_NE Wake-Up Enable for RX FIFO Not Empty 0 1 RX_FULL Wake-Up Enable for RX FIFO Full 1 1 RX_THD Wake-Up Enable for RX FIFO Threshold Met 2 1 WKFL Wake up Flags register 0x0038 RX_NE Wake-Up Flag for RX FIFO Not Empty 0 1 RX_FULL Wake-Up Flag for RX FIFO Full 1 1 RX_THD Wake-Up Flag for RX FIFO Threshold Met 2 1 UART1 UART Low Power Registers 1 0x40043000 UART2 UART Low Power Registers 2 0x40044000 UART3 UART Low Power Registers 3 0x40145000 WDT Windowed Watchdog Timer 0x40003000 0x00 0x0400 registers WWDT 1 CTRL Watchdog Timer Control Register. 0x00 read-write INT_LATE_VAL Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_LATE_VAL Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 4 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 EN Windowed Watchdog Timer Enable. 8 1 dis Disable. 0 en Enable. 1 INT_LATE Windowed Watchdog Timer Interrupt Flag Too Late. 9 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 WDT_INT_EN Windowed Watchdog Timer Interrupt Enable. 10 1 dis Disable. 0 en Enable. 1 WDT_RST_EN Windowed Watchdog Timer Reset Enable. 11 1 dis Disable. 0 en Enable. 1 INT_EARLY Windowed Watchdog Timer Interrupt Flag Too Soon. 12 1 read-write inactive No interrupt is pending. 0 pending An interrupt is pending. 1 INT_EARLY_VAL Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 16 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_EARLY_VAL Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. 20 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 CLKRDY_IE Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock. 27 1 CLKRDY Clock Status. 28 1 WIN_EN Enables the Windowed Watchdog Function. 29 1 dis Windowed Mode Disabled (i.e. Compatibility Mode). 0 en Windowed Mode Enabled. 1 RST_EARLY Windowed Watchdog Timer Reset Flag Too Soon. 30 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST_LATE Windowed Watchdog Timer Reset Flag Too Late. 31 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST Windowed Watchdog Timer Reset Register. 0x04 write-only RESET Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled. 0 8 seq0 The first value to be written to reset the WDT. 0x000000A5 seq1 The second value to be written to reset the WDT. 0x0000005A CLKSEL Windowed Watchdog Timer Clock Select Register. 0x08 read-write SOURCE WWDT Clock Selection Register. 0 3 CNT Windowed Watchdog Timer Count Register. 0x0C read-only COUNT Current Value of the Windowed Watchdog Timer Counter. 0 32 WDT1 Windowed Watchdog Timer 1 0x40003400 WDT1 WDT1 IRQ 57