Maxim-Integrated Maxim max32650 ARMCM4 1.0 MAX32650. CM4 r2p1 little true true 3 false 8 32 0x20 read-write 0x00000000 0xFFFFFFFF ADC 10-bit Analog to Digital Converter 0x40034000 32 read-write 0 0x1000 registers ADC ADC IRQ 20 CTRL ADC Control 0x0000 read-write start Start ADC Conversion [0:0] read-write inactive 0 start 1 pwr ADC Power Up [1:1] read-write adc_off 0 adc_on 1 refbuf_pwr ADC Reference Buffer Power Up [3:3] read-write refbuf_off 0 refbuf_on 1 ref_sel ADC Reference Select [4:4] read-write bandgap 0 vdd_div2 1 ref_scale ADC Reference Scale [8:8] read-write div1 0 div2 1 input_scale ADC Scale [9:9] read-write div1 0 div2 1 clk_en ADC Clock Enable [11:11] read-write dis 0 en 1 ch_sel ADC Channel Select [15:12] read-write ain0 0 ain1 1 ain2 2 ain3 3 ain0_div5 4 ain1_div5 5 vddb_div4 6 vdda 7 vcore 8 vrtc_div2 9 rsv_0xa 10 vddio_div4 11 vddioh_div4 12 data_align ADC Data Alignment Select [17:17] read-write lsb_justified 0 msb_justified 1 STATUS ADC Status 0x0004 read-write active ADC Conversion In Progress [0:0] read-only idle 0 active 1 pwr_up_active AFE Power Up Delay Active [2:2] read-only no_delay 0 delay_active 1 overflow ADC Overflow [3:3] read-only underflow 0 overflow 1 DATA ADC Output Data 0x0008 read-write data ADC Converted Sample Data Output [15:0] read-only INTR ADC Interrupt Control Register 0x000C read-write done_ie ADC Done Interrupt Enable [0:0] read-write dis 0 en 1 ref_ready_ie ADC Reference Ready Interrupt Enable [1:1] read-write dis 0 en 1 hi_limit_ie ADC Hi Limit Monitor Interrupt Enable [2:2] read-write dis 0 en 1 lo_limit_ie ADC Lo Limit Monitor Interrupt Enable [3:3] read-write dis 0 en 1 overflow_ie ADC Overflow Interrupt Enable [4:4] read-write dis 0 en 1 done_if ADC Done Interrupt Flag [16:16] read-write oneToClear inactive 0 active 1 ref_ready_if ADC Reference Ready Interrupt Flag [17:17] read-write oneToClear inactive 0 active 1 hi_limit_if ADC Hi Limit Monitor Interrupt Flag [18:18] read-write oneToClear inactive 0 active 1 lo_limit_if ADC Lo Limit Monitor Interrupt Flag [19:19] read-write oneToClear inactive 0 active 1 overflow_if ADC Overflow Interrupt Flag [20:20] read-write oneToClear inactive 0 active 1 pending ADC Interrupt Pending Status [22:22] read-only no_int 0 int_pending 1 4 4 LIMIT[%s] ADC Limit 0x0010 read-write ch_lo_limit Low Limit Threshold [9:0] read-write ch_hi_limit High Limit Threshold [21:12] read-write ch_sel ADC Channel Select [27:24] read-write ain0 0 ain1 1 ain2 2 ain3 3 ain4 4 ain5 5 ain6 6 ain7 7 ain8 8 ain9 9 ain10 10 ain11 11 ain12 12 ch_lo_limit_en Low Limit Monitoring Enable [28:28] read-write dis 0 en 1 ch_hi_limit_en High Limit Monitoring Enable [29:29] read-write dis 0 en 1 AESKEYS AES Key Registers. 0x40005000 0x00 0x400 registers 4 4 KEY0[%s] AES Key 0. 0x00 32 4 4 KEY1[%s] AES Key 1. 0x20 32 4 4 KEY2[%s] AES Key 2. 0x100 32 4 4 KEY3[%s] AES Key 3. 0x180 32 CLCD Color LCD Controller 0x40031000 0x00 0xFFF registers CLK_CTRL LCD Clock Control Register 0x000 LCD_CLKDIV Clock divsor 0 8 STN_AC_BIAS AC Bias Frequency Control. THis fiels sets the AC Bias Frequency output on the CLCD_VDEN pin for Color StN display mode. 8 8 VDEN_POL CLCD_VDEN Polarity Selection. This field sets the polarity of the video enable signal output pin. 16 1 ACTIVELO Active Low 0 ACTIVEHI Active High 1 VSYNC_POL VSYNC Polarity Selection. This field sets the polarity of the vertical sync signal output pin. 17 1 ACTIVELO Active Low 0 ACTIVEHI Active Hi 1 HSYNC_POL HSYNC Polarity Selection. This field sets the polarity of the horizontal sync signal output pin. 18 1 ACTIVELO Active Low 0 ACTIVEHI Active Hi 1 CLK_EDGE_SEL Clock Edge Selection. This field controls the clock edge that is used by the LCD panel to sample the data and signal lines. 19 1 RISING Rising edge 0 FALLING Falling Edge 1 CLK_ACTIVE Clock Active on Data. If the display type is Color STN 8-bit, this bit selects if the CLCD_CLK output is active always or only during data output to the display. 20 1 ALWAYS Always Active 0 ONDATA ACTIVE ON DATA 1 VTIM_0 LCD Vertical Timing 0 Register 0x004 VLINES V Lines 0 8 VBP_WIDTH V BACK PORCH 16 8 VTIM_1 LCD Vertical Timing 1 Register 0x008 VSYNC_WIDTH V Sync Width 0 8 VFP_WIDTH V Front PORCH 16 8 HTIM LCD Horizontal Timing Register. 0x00C HSYNC_WIDTH Horizontal Sync Width in CLCD Clocks from 1 to 256 HSync Width = HSYNCWIDTH+1 Clocks 0 8 HFP_WIDTH Horizontal Front Porch size in lines from 1 to 256 8 8 HSIZE_INDEX Horizontal Front Porch Size in Pixels = (HSIZE + 1) *16 16 8 HBP_WIDTH Horizontal Back Porch size in CLCD Clocks from 1 to 256 -> HBP= (HBACKPORCH+1) 24 8 CTRL LCD Control Register 0x010 CLCD_ENABLE LCD Enable 0 1 dis Disable 0 en Enable 1 VCI_SEL Vertical Compare Interrupt Source Select 1 2 ON_VSYNC On Vertical Sync 0 ON_VBP On Vertical Back Porch 1 ON_VDEN On Active Video 2 ON_VFP On Vertical Front Porch 3 DISPTYPE Display Type 4 4 8BITCOLORSTN STN Color 8 bit 4 TFT TFT 8 BPP BPP 8 3 BPP1 BPP 1 0 BPP2 BPP 2 1 BPP4 BPP 4 2 BPP8 BPP 8 3 BPP16 BPP 16 4 BPP24 BPP 24 5 MODE565 MODE565 11 1 BGR556 MODE 556 0 RGB565 MODE 565 1 ENDIAN EMODE 12 2 LBLP LLBP 0 BBBP BBBP 1 LBBP LBBP 2 RFU RFU 3 COMPACT_24b C24 15 1 1_PFR 1 pixel per frame buffer entry 0 1ANDA3RD_PFR 1 and 1/3 pixels per fram buffer entry 1 BURST_SIZE BURST 19 2 4WORDS 4 32-bit words. 0 8WORDS 8 32-bit words. 1 16WORDS 16 32-bit words. 2 LEND_POL LEND Polarity Selection. This field sets the polarity of the line end signal output pin. 21 1 ACTIVELO Active Low 0 ACTIVEHI Active High 1 PWR_ENABLE Display Power Enable. Enables power to the display using the PWREN output pin. 22 1 LO Power enable pin is set low. 0 HI Power enable pin is set high. 1 FRBUF Frame buffer. 0x18 FRAME_ADDR Set this field to the beginning of the fram buffer data to display. 0 32 INT_EN LCD Interrupt Enable Register. 0x020 UNDERFLOW_IE Under FLow Interupt Enable 0 1 dis Interrupt disabled. 0 en Interrupt enabled. 1 ADDR_RDY_IE Address Ready Interupt Enable 1 1 dis Interrupt disabled. 0 en Interrupt enabled. 1 VCI_IE VCI Interupt Enable 2 1 dis Interrupt disabled. 0 en Interrupt enabled. 1 BUS_ERROR_IE BERR Interupt Enable 3 1 dis Interrupt disabled. 0 en Interrupt enabled. 1 INT_STAT LCD Status Register. 0x024 oneToClear UNDERFLOW Under FLow Interupt Status 0 1 read inactive No interrupt pending 0 pend Interrupt pending 1 write clear Clears the interrupt flag 1 ADDR_RDY Address Ready Interupt Status 1 1 read inactive No interrupt pending 0 pend Interrupt pending 1 write clear Clears the interrupt flag 1 VCI VCI Interupt Status 2 1 read inactive No interrupt pending 0 pend Interrupt pending 1 write clear Clears the interrupt flag 1 BUS_ERROR BERR Interupt Status 3 1 read inactive No interrupt pending 0 pend Interrupt pending 1 write clear Clears the interrupt flag 1 CLCD_IDLE LCD IDLE Staus 8 1 IDLE Idle. 0 BUSY Busy. 1 256 4 PALETTE_RAM[%s] Palette 0x400 RED Red Data for Pallet Entry. 0 8 GREEN Green Data for Pallet Entry. 8 8 BLUE Blue Data for Pallet Entry. 16 8 DMA DMA Controller Fully programmable, chaining capable DMA channels. 0x40028000 32 0x00 0x1000 registers DMA0 28 DMA1 29 DMA2 30 DMA3 31 DMA4 68 DMA5 69 DMA6 70 DMA7 71 DMA8 72 DMA9 73 DMA10 74 DMA11 75 DMA12 76 DMA13 77 DMA14 78 DMA15 79 CN DMA Control Register. 0x000 CH0_IEN Channel 0 Interrupt Enable. 0 1 dis Disable. 0 en Enable. 1 CH1_IEN Channel 1 Interrupt Enable. 1 1 dis Disable. 0 en Enable. 1 CH2_IEN Channel 2 Interrupt Enable. 2 1 dis Disable. 0 en Enable. 1 CH3_IEN Channel 3 Interrupt Enable. 3 1 dis Disable. 0 en Enable. 1 CH4_IEN Channel 4 Interrupt Enable. 4 1 dis Disable. 0 en Enable. 1 CH5_IEN Channel 5 Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 CH6_IEN Channel 6 Interrupt Enable. 6 1 dis Disable. 0 en Enable. 1 CH7_IEN Channel 7 Interrupt Enable. 7 1 dis Disable. 0 en Enable. 1 CH8_IEN Channel 8 Interrupt Enable. 8 1 dis Disable. 0 en Enable. 1 CH9_IEN Channel 9 Interrupt Enable. 9 1 dis Disable. 0 en Enable. 1 CH10_IEN Channel 10 Interrupt Enable. 10 1 dis Disable. 0 en Enable. 1 CH11_IEN Channel 11 Interrupt Enable. 11 1 dis Disable. 0 en Enable. 1 CH12_IEN Channel 12 Interrupt Enable. 12 1 dis Disable. 0 en Enable. 1 CH13_IEN Channel 13 Interrupt Enable. 13 1 dis Disable. 0 en Enable. 1 CH14_IEN Channel 14 Interrupt Enable. 14 1 dis Disable. 0 en Enable. 1 CH15_IEN Channel 15 Interrupt Enable. 15 1 dis Disable. 0 en Enable. 1 INTR DMA Interrupt Register. 0x004 read-only CH0_IPEND Channel 0 Interrupt Pending. 0 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH1_IPEND Channel 1 Interrupt Pending. 1 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH2_IPEND Channel 2 Interrupt Pending. 2 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH3_IPEND Channel 3 Interrupt Pending. 3 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH4_IPEND Channel 4 Interrupt Pending. 4 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH5_IPEND Channel 5 Interrupt Pending. 5 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH6_IPEND Channel 6 Interrupt Pending. 6 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH7_IPEND Channel 7 Interrupt Pending. 7 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH8_IPEND Channel 8 Interrupt Pending. 8 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH9_IPEND Channel 9 Interrupt Pending. 9 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH10_IPEND Channel 10 Interrupt Pending. 10 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH11_IPEND Channel 11 Interrupt Pending. 11 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH12_IPEND Channel 12 Interrupt Pending. 12 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH13_IPEND Channel 13 Interrupt Pending. 13 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH14_IPEND Channel 14 Interrupt Pending. 14 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 CH15_IPEND Channel 15 Interrupt Pending. 15 1 inactive Channel interrupt not currently asserted. 0 pending Channel interrupt pending. 1 16 0x20 CH[%s] DMA Channel registers. dma_ch 0x100 read-write CFG DMA Channel Configuration Register. 0x000 CHEN Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 RLDEN Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. 1 1 dis Disable. 0 en Enable. 1 PRI DMA Priority. 2 2 high Highest Priority. 0 medHigh Medium High Priority. 1 medLow Medium Low Priority. 2 low Lowest Priority. 3 REQSEL Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. 4 6 MEMTOMEM Memory To Memory 0x00 SPI0RX SPI0 RX 0x01 SPI1RX SPI1 RX 0x02 SPI2RX SPI2 RX 0x03 UART0RX UART0 RX 0x04 UART1RX UART1 RX 0x05 I2C0RX I2C0 RX 0x07 I2C1RX I2C1 RX 0x08 ADC Analog-to-Digital Converter Channel 0x09 UART2RX UART2 RX 0x0E SPI3RX SPI3 RX 0x0F SPIMSSRX SPIMSS RX 0x10 USBRXEP1 USB Endpoint 1 RX 0x11 USBRXEP2 USB Endpoint 2 RX 0x12 USBRXEP3 USB Endpoint 3 RX 0x13 USBRXEP4 USB Endpoint 4 RX 0x14 USBRXEP5 USB Endpoint 5 RX 0x15 USBRXEP6 USB Endpoint 6 RX 0x16 USBRXEP7 USB Endpoint 7 RX 0x17 USBRXEP8 USB Endpoint 8 RX 0x18 USBRXEP9 USB Endpoint 9 RX 0x19 USBRXEP10 USB Endpoint 10 RX 0x1A USBRXEP11 USB Endpoint 11 RX 0x1B SPI0TX SPI0 TX 0x21 SPI1TX SPI1 TX 0x22 SPI2TX SPI2 TX 0x23 UART0TX UART0 TX 0x24 UART1TX UART1 TX 0x25 I2C0TX I2C0 TX 0x27 I2C1TX I2C1 TX 0x28 UART2TX UART2 TX 0x2E SPI3TX SPI3 TX 0x2F SPIMSSTX SPIMSS TX 0x30 USBTXEP1 USB Endpoint 1 TX 0x31 USBTXEP2 USB Endpoint 2 TX 0x32 USBTXEP3 USB Endpoint 3 TX 0x33 USBTXEP4 USB Endpoint 4 TX 0x34 USBTXEP5 USB Endpoint 5 TX 0x35 USBTXEP6 USB Endpoint 6 TX 0x36 USBTXEP7 USB Endpoint 7 TX 0x37 USBTXEP8 USB Endpoint 8 TX 0x38 USBTXEP9 USB Endpoint 9 TX 0x39 USBTXEP10 USB Endpoint 10 TX 0x3A USBTXEP11 USB Endpoint 11 TX 0x3B REQWAIT Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. 10 1 normal Normal timer start. 0 delay Delay timer start. 1 TOSEL Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock. 11 3 to4 Timeout of 3 to 4 prescale clocks. 0 to8 Timeout of 7 to 8 prescale clocks. 1 to16 Timeout of 15 to 16 prescale clocks. 2 to32 Timeout of 31 to 32 prescale clocks. 3 to64 Timeout of 63 to 64 prescale clocks. 4 to128 Timeout of 127 to 128 prescale clocks. 5 to256 Timeout of 255 to 256 prescale clocks. 6 to512 Timeout of 511 to 512 prescale clocks. 7 PSSEL Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. 14 2 dis Disable timer. 0 div256 hclk / 256. 1 div64k hclk / 64k. 2 div16M hclk / 16M. 3 SRCWD Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. 16 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 SRINC Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. 18 1 dis Disable. 0 en Enable. 1 DSTWD Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). 20 2 byte Byte. 0 halfWord Halfword. 1 word Word. 2 DSTINC Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. 22 1 dis Disable. 0 en Enable. 1 BRST Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. 24 5 CHDIEN Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. 30 1 dis Disable. 0 en Enable. 1 CTZIEN Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. 31 1 dis Disable. 0 en Enable. 1 ST DMA Channel Status Register. 0x004 CH_ST Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). 0 1 read-only disabled Disabled. 0 enabled Enabled. 1 IPEND Channel Interrupt. 1 1 read-only inactive No interrupt is pending. 0 pending An interrupt is pending. 1 CTZ_ST Count-to-Zero (CTZ) Status 2 1 oneToClear ctz_st_enum_rd read noEvent The event has not occurred. 0 ctz_occur The event has occurred. 1 ctz_st_enum_wr write Clear Clears the interrupt flag 1 RLD_ST Reload Status. 3 1 oneToClear read noEvent The event has not occurred. 0 reloaded The event has occurred. 1 write Clear Clears the interrupt flag 1 BUS_ERR Bus Error. Indicates that an AHB abort was received and the channel has been disabled. 4 1 oneToClear read noEvent The event has not occurred. 0 bus_err The event has occurred. 1 write Clear Clears the interrupt flag 1 TO_ST Time-Out Status. 6 1 oneToClear read noEvent The event has not occurred. 0 expired The event has occurred. 1 write Clear Clears the interrupt flag 1 SRC Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. 0x008 ADDR 0 32 DST Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. 0x00C ADDR 0 32 CNT DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. 0x010 CNT DMA Counter. 0 24 SRC_RLD Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. 0x014 SRC_RLD Source Address Reload Value. 0 31 DST_RLD Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. 0x018 DST_RLD Destination Address Reload Value. 0 31 CNT_RLD DMA Channel Count Reload Register. 0x01C CNT_RLD Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. 0 24 RLDEN Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. 31 1 dis Disable. 0 en Enable. 1 EMCC External Memory Cache Controller Registers. 0x40033000 0x00 0x1000 registers CACHE_ID Cache ID Register. 0x0000 read-only RELNUM Release Number. Identifies the RTL release version. 0 6 PARTNUM Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. 6 4 CCHID Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. 10 6 MEM_SIZE Memory Configuration Register. 0x0004 read-only 0x00080008 CCHSZ Cache Size. Indicates total size in Kbytes of cache. 0 16 MEMSZ Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. 16 16 CACHE_CTRL Cache Control and Status Register. 0x0100 ENABLE Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. 0 1 dis Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. 0 en Cache Enabled. 1 WRITE_ALLOC Write Allocate Enable. This bit only writable while the cache is disabled. 1 1 dis Write-no-allocate. 0 en Write-allocate enabled. 1 CWFST_DIS Critical word first and streaming disable. This bit only writeable while the cache is disabled. 2 1 dis Critical word first and streaming disabled. 1 en Critical word first and streaming enabled. 0 READY Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. 16 1 notReady Not Ready. 0 ready Ready. 1 INVALIDATE Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0. 0x0700 IA Invalidate all cache contents. 0 32 FLC Flash Memory Control. FLSH_ 0x40029000 0x00 0x1000 registers Flash_Controller Flash Controller interrupt. 23 ADDR Flash Write Address. 0x00 ADDR Address for next operation. 0 32 CLKDIV Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. 0x04 0x00000064 CLKDIV Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. 0 8 CTRL Flash Control Register. 0x08 WRITE Write. This bit is automatically cleared after the operation. 0 1 complete No operation/complete. 0 start_wr Start operation. 1 MASS_ERASE Mass Erase. This bit is automatically cleared after the operation. 1 1 complete No operation/complete. 0 start_me Start operation. 1 PAGE_ERASE Page Erase. This bit is automatically cleared after the operation. 2 1 complete No operation/complete. 0 start_pge Start operation. 1 WIDTH This field sets the width of a write to the flash page. Select between 128-bit (default) and 32-bit. 4 1 128_bit Flash is written to in 128-bit increments. 0 32_bit Flash is written to in 32-bit increments. 1 ERASE_CODE Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. 8 8 dis Flash erases disabled. 0 pge Enable Page Erase. 0x55 me Enable Mass Erase. The debug port must be enabled. 0xAA BUSY Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. 24 1 read-only idle Idle. 0 busy Busy. 1 UNLOCK_CODE Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. 28 4 unlocked Flash Unlocked. 2 locked Flash Locked. 3 INTR Flash Interrupt Register. 0x024 DONE Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. 0 1 inactive No interrupt is pending. 0 pending An interrupt is pending. 1 ACCESS_FAIL Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. 1 1 noerr No Failure. 0 error Failure occurs. 1 DONE_IE Flash Done Interrupt Enable. 8 1 dis Disable. 0 en Enable. 1 ACCESS_FAIL_IE 9 1 dis Disable. 0 en Enable. 1 4 4 DATA[%s] Flash Write Data. 0x30 DATA Data next operation. 0 32 ACTNL Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. 0x40 write-only ACNTL Access control. 0 32 GPIO0 Individual I/O for each GPIO GPIO 0x40008000 0x00 0x1000 registers GPIO0 GPIO0 interrupt. 24 EN GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. 0x00 GPIO_EN Mask of all of the pins on the port. 0 32 alternate Alternate function enabled. 0 GPIO GPIO function is enabled. 1 EN_SET GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. 0x04 GPIO_EN_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_EN register. 1 EN_CLR GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. 0x08 GPIO_EN_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_EN register. 1 OUT_EN GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. 0x0C GPIO_OUT_EN Mask of all of the pins on the port. 0 32 dis GPIO Output Disable 0 en GPIO Output Enable 1 OUT_EN_SET GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. 0x10 GPIO_OUT_EN_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_OUT_EN register. 1 OUT_EN_CLR GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. 0x14 GPIO_OUT_EN_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_OUT_EN register. 1 OUT GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. 0x18 GPIO_OUT Mask of all of the pins on the port. 0 32 low Drive Logic 0 (low) on GPIO output. 0 high Drive logic 1 (high) on GPIO output. 1 OUT_SET GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. 0x1C write-only GPIO_OUT_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_OUT register. 1 OUT_CLR GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. 0x20 write-only GPIO_OUT_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_OUT register. 1 IN GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. 0x24 read-only GPIO_IN Mask of all of the pins on the port. 0 32 low Logic 0 (low) on GPIO input. 0 high Logic 1 (high) on GPIO input. 1 INT_MODE GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. 0x28 GPIO_INT_MODE Mask of all of the pins on the port. 0 32 level Interrupts for this pin are level triggered. 0 edge Interrupts for this pin are edge triggered. 1 INT_POL GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. 0x2C GPIO_INT_POL Mask of all of the pins on the port. 0 32 falling Interrupts are latched on a falling edge or low level condition for this pin. 0 rising Interrupts are latched on a rising edge or high condition for this pin. 1 IN_EN GPIO Port Input Enable. 0x30 GPIO_IN_EN Mask of all of the pins on the port. 0 32 dis GPIO Input Disable 0 en GPIO Input Enable 1 INT_EN GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. 0x34 GPIO_INT_EN Mask of all of the pins on the port. 0 32 dis Interrupts are disabled for this GPIO pin. 0 en Interrupts are enabled for this GPIO pin. 1 INT_EN_SET GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. 0x38 GPIO_INT_EN_SET Mask of all of the pins on the port. 0 32 no No Effect. 0 set Set GPIO_INT_EN bit in this position to '1' 1 INT_EN_CLR GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. 0x3C GPIO_INT_EN_CLR Mask of all of the pins on the port. 0 32 no No Effect. 0 clear Clear GPIO_INT_EN bit in this position to '0' 1 INT_STAT GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. 0x40 read-only GPIO_INT_STAT Mask of all of the pins on the port. 0 32 no No Interrupt is pending on this GPIO pin. 0 pending An Interrupt is pending on this GPIO pin. 1 INT_CLR GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. 0x48 GPIO_INT_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_INT_STAT register. 1 WAKE_EN GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. 0x4C GPIO_WAKE_EN Mask of all of the pins on the port. 0 32 dis PMU wakeup for this GPIO is disabled. 0 en PMU wakeup for this GPIO is enabled. 1 WAKE_EN_SET GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. 0x50 GPIO_WAKE_EN_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_WAKE_EN register. 1 WAKE_EN_CLR GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. 0x54 GPIO_WAKE_EN_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_WAKE_EN register. 1 INT_DUAL_EDGE GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. 0x5C GPIO_INT_DUAL_EDGE Mask of all of the pins on the port. 0 32 no No Effect. 0 dual Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. 1 PDPU_SEL0 GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. 0x60 GPIO_PDPU_SEL0 The two bits in GPIO_PDPU_SEL0 and GPIO_PDPU_SEL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pu Pull-up mode. 1 PDPU_SEL1 GPIO Input Mode Config 2. Each bit in this register enables the pull-down for the associated GPIO pin in this port. 0x64 GPIO_PDPU_SEL1 The two bits in GPIO_PDPU_SEL0 and GPIO_PDPU_SEL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. 0 32 impedance High Impedance. 0 pd Pull-down mode. 1 AF_SEL GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. 0x68 GPIO_AF_SEL Mask of all of the pins on the port. 0 32 primary Primary function selected. 0 secondary Secondary function selected. 1 AF_SEL_SET GPIO Alternate Function Selectset. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. 0x6C AF_SEL_SET Mask of all of the pins on the port. 0 32 no No effect. 0 set Set the corresponding bit in GPIO_AF_SEL register. 1 AF_SEL_CLR GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. 0x70 GPIO_AF_SEL_CLR Mask of all of the pins on the port. 0 32 no No effect. 0 clear Clear the corresponding bit in GPIO_AF_SEL register. 1 DS_SEL0 GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. The total drive strength multiplier is the multiplication between the two drive strength select registers. 0xB0 GPIO_DS_SEL0 Mask of all of the pins on the port. 0 32 1X 1 x GPIO_DS_SEL1 = total drive strength multiplier. 0 2X 2 x GPIO_DS_SEL1 = total drive strength multiplier. 1 DS_SEL1 GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. The total drive strength multiplier is the multiplication between the two drive strength select registers. 0xB4 GPIO_DS_SEL1 Mask of all of the pins on the port. 0 32 1X 1 x GPIO_DS_SEL0 = total drive strength multiplier. 0 4X 4 x GPIO_DS_SEL0 = total drive strength multiplier. 1 PSSEL GPIO Pull Select Mode. 0xB8 GPIO_PSSEL Mask of all of the pins on the port. 0 32 WEAK_PDPU 1MOhm Pull-Up/Down resistor connected to the input pin. 0 STRONG_PDPU 25KOhm Pull-Up/Down resistor connected to the input pin. 1 VSSEL GPIO Voltage Select. 0xC0 GPIO_VSSEL Mask of all of the pins on the port. 0 32 VDDIO Vddio set as the pin's supply voltage. 0 VDDIOH Vddioh set as the pin's supply voltage. 1 GPIO1 Individual I/O for each GPIO 1 0x40009000 GPIO1 GPIO1 IRQ 25 GPIO2 Individual I/O for each GPIO 2 0x4000A000 GPIO2 GPIO2 IRQ 26 GPIO3 Individual I/O for each GPIO 3 0x4000B000 GPIO3 GPIO3 IRQ 58 HPB HyperBus Memory Controller 0x40039000 0x00 0x1000 registers HPB HPB interrupt. 61 STATUS HPB Status Register. 0x00 0x00000000 RACT Read transaction in progress. 0 1 noRead No read transaction in progress. 0 read Read transaction in progress. 1 RDECERR Read address error. 8 1 noErr No error. 0 err Error. 1 RRSTOERR Reset during read error. 10 1 noErr No error. 0 err Error. 1 RDSSTALL Read data stall. 11 1 normalop Read operation normal. 0 stalled Read stalled. 1 WACT Write transaction in progress. 16 1 noWrite No write transaction in progress. 0 write Write transaction in progress. 1 WDECERR Write address error. 24 1 noErr No error. 0 err Error. 1 WRSTOERR Reset during write error. 26 1 noErr No error. 0 err Error. 1 INTEN HPB Interrupt Enable. 0x04 0x00000000 ERRINTE Error interrupt enable. 1 1 dis Disable error interrupt. 0 en Enable error interrupt. 1 INTFL HPB Interrupt Status Flags. 0x08 0x00000000 ERRINT Error interrupt status flags. 1 1 noInt No interrupt pending. 0 pending Error interrupt pending. 1 2 4 MBR[%s] HPB Memory Base Address. 0x10 0x00000000 ADDR Memory Base Address. 24 8 2 4 MCR[%s] HPB Memory Configuration Register. 0x20 0x00000000 DEV_TYPE Memory device type select. 3 2 hyperFlash HyperFlash. 0 xccelaPSRAM Xccela PSRAM. 1 hyperRAM HyperRAM. 2 CRT Configuration register target select. 5 1 mem_space Access memory space. 0 config_reg_space Access configuration register space. 1 READ_LATENCY Xccela fixed read latency enable. 6 1 variable Variable read latency. 0 fixed Fixed read latency. 1 HSE Xccela half sleep exit. 7 1 dis Half-Sleep exit disabled. 0 en Half-Sleep exit enabled. 1 MAXLEN Maximum read/write.. 18 9 MAXLEN_EN Maximum CS# length enable. 31 1 dis Configurable CS# low time disabled. 0 en Configurable CS# low time enabled. 1 2 4 MTR[%s] HPB Memory Timing Register. 0x30 0x00000000 LATENCY RAM Latency Clock Cycles. 0 4 5CLK 5 clock cycles. 0 6CLK 6 clock cycles. 1 3CLK 3 clock cycles. 14 4CLK 4 clock cycles. 15 WCSH Write chip select hold after CK falling edge. 8 4 RCSH Read chip select hold after CK falling edge. 12 4 WCSS Write chip select setup time to next CK rising edge. 16 4 RCSS Read chip select setup time to next CK rising edge. 20 4 WCSHI Write chip select high between operations. 24 4 RCSHI Read chip select high between operations. 28 4 I2C0 Inter-Integrated Circuit. I2C 0x4001D000 32 0x00 0x1000 registers I2C0 I2C0 IRQ 13 CTRL0 Control Register 0. 0x00 I2CEN I2C Enable. [0:0] read-write dis Disable I2C. 0 en enable I2C. 1 MST Master Mode Enable. [1:1] read-write slave_mode Slave Mode. 0 master_mode Master Mode. 1 GCEN General Call Address Enable. [2:2] read-write dis Ignore Gneral Call Address. 0 en Acknowledge general call address. 1 IRXM Interactive Receive Mode. [3:3] read-write dis Disable Interactive Receive Mode. 0 en Enable Interactive Receive Mode. 1 ACK Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. [4:4] read-write ack return ACK (pulling SDA LOW). 0 nack return NACK (leaving SDA HIGH). 1 SCL_OUT SCL Output. This bits control SCL output when SWOE =1. [6:6] read-write low Drive SCL low. 0 high Release SCL. 1 SDA_OUT SDA Output. This bits control SDA output when SWOE = 1. [7:7] read-write low Drive SDA low. 0 high Release SDA. 1 SCL SCL status. This bit reflects the logic gate of SCL signal. [8:8] read-only low SCL pin is logic low. 0 high SCL pin is logic high. 1 SDA SDA status. THis bit reflects the logic gate of SDA signal. [9:9] read-only low SDA pin is logic low. 0 high SDA pin is logic high. 1 SWOE Software Output Enable. [10:10] read-write dis I2C Outputs SCLO and SDAO disabled. 0 en I2C Outputs SCLO and SDAO enabled. 1 READ Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. [11:11] read-only write Write. 0 read Read. 1 SCL_STRD This bit will disable slave clock stretching when set. [12:12] read-write en Slave clock stretching enabled. 0 dis Slave clock stretching disabled. 1 SCL_PPM SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. [13:13] read-write dis Standard open-drain operation: drive low for 0, Hi-Z for 1 0 en Non-standard push-pull operation: drive low for 0, drive high for 1 1 STAT Status Register. 0x04 BUSY Bus transaction active status bit. [0:0] read-only idle I2C Bus Idle. 0 busy I2C Bus Busy. 1 RXE RX FIFO empty. [1:1] read-only not_empty Not Empty. 0 empty Empty. 1 RXF RX FIFO full. [2:2] read-only not_full Not Full. 0 full Full. 1 TXE TX FIFO empty. [3:3] not_empty Not Empty. 0 empty Empty. 1 TXF TX FIFO full. [4:4] not_full Not Full. 0 full Full. 1 CKMD SCL Drive Status. [5:5] read-only scl_not_active Device not actively driving SCL clock cycles. 0 scl_active Device operating as master and actively driving SCL clock cycles. 1 INT_FL0 Interrupt Status Register. 0x08 DONEI Transfer Done Interrupt. [0:0] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 IRXMI Interactive Receive Interrupt. [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 GCI Slave General Call Address Match Interrupt. [2:2] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 AMI Slave Address Match Interrupt. [3:3] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 RXTHI Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. [4:4] inactive No interrupt is pending. 0 pending An interrupt is pending. RX_FIFO equal or more bytes than the threshold. 1 TXTHI Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. [5:5] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 STOPI STOP Interrupt. [6:6] inactive No interrupt is pending. 0 pending An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 ADRACKI Address Acknowledge Interrupt. [7:7] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ARBERI Arbritation error Interrupt. [8:8] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TOERI timeout Error Interrupt. [9:9] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 ADRERI Address NACK Error Interrupt. [10:10] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DATAERI Data NACK Error Interrupt. [11:11] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 DNRERI Do Not Respond Error Interrupt. [12:12] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 STRTERI Start Error Interrupt. [13:13] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 STOPERI Stop Error Interrupt. [14:14] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TXLOI Transmit Lock Out Interrupt. [15:15] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 INT_EN0 Interrupt Enable Register. 0x0C read-write DONEIE Transfer Done Interrupt Enable. [0:0] read-write dis Interrupt disabled. 0 en Interrupt enabled when DONE = 1. 1 IRXMIE Description not available. [1:1] read-write dis Interrupt disabled. 0 en Interrupt enabled when RX_MODE = 1. 1 GCIE Slave mode general call address match received input enable. [2:2] read-write dis Interrupt disabled. 0 en Interrupt enabled when GEN_CTRL_ADDR = 1. 1 AMIE Slave mode incoming address match interrupt. [3:3] read-write dis Interrupt disabled. 0 en Interrupt enabled when ADDR_MATCH = 1. 1 RXTHIE RX FIFO Above Treshold Level Interrupt Enable. [4:4] read-write dis Interrupt disabled. 0 en Interrupt enabled. 1 TXTHIE TX FIFO Below Treshold Level Interrupt Enable. [5:5] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOPIE Stop Interrupt Enable [6:6] read-write dis Interrupt disabled. 0 en Interrupt enabled when STOP = 1. 1 ADRACKIE Received Address ACK from Slave Interrupt. [7:7] dis Interrupt disabled. 0 en Interrupt enabled. 1 ARBERIE Master Mode Arbitration Lost Interrupt. [8:8] dis Interrupt disabled. 0 en Interrupt enabled. 1 TOERIE Timeout Error Interrupt Enable. [9:9] dis Interrupt disabled. 0 en Interrupt enabled. 1 ADRERIE Master Mode Address NACK Received Interrupt. [10:10] dis Interrupt disabled. 0 en Interrupt enabled. 1 DATAERIE Master Mode Data NACK Received Interrupt. [11:11] dis Interrupt disabled. 0 en Interrupt enabled. 1 DNRERIE Slave Mode Do Not Respond Interrupt. [12:12] dis Interrupt disabled. 0 en Interrupt enabled. 1 STRTERIE Out of Sequence START condition detected interrupt. [13:13] dis Interrupt disabled. 0 en Interrupt enabled. 1 STOPERIE Out of Sequence STOP condition detected interrupt. [14:14] dis Interrupt disabled. 0 en Interrupt enabled. 1 TXLOIE TX FIFO Locked Out Interrupt. [15:15] dis Interrupt disabled. 0 en Interrupt enabled. 1 INT_FL1 Interrupt Status Register 1. 0x10 RXOFI Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. [0:0] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 TXUFI Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). [1:1] inactive No Interrupt is Pending. 0 pending An interrupt is pending. 1 INT_EN1 Interrupt Staus Register 1. 0x14 read-write RXOFIE Receiver Overflow Interrupt Enable. [0:0] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 TXUFIE Transmit Underflow Interrupt Enable. [1:1] dis No Interrupt is Pending. 0 en An interrupt is pending. 1 FIFO_LEN FIFO Configuration Register. 0x18 RXLEN Receive FIFO Length. [7:0] read-only TXLEN Transmit FIFO Length. [15:8] read-only RX_CTRL0 Receive Control Register 0. 0x1C DNR Do Not Respond. [0:0] respond Always respond to address match. 0 dont_respond Do not respond to address match when RX_FIFO is not empty. 1 RXFSH Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. [7:7] not_flushed FIFO not flushed. 0 flush Flush RX_FIFO. 1 RXTH Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. [11:8] RX_CTRL1 Receive Control Register 1. 0x20 RXCNT Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. [7:0] RXFIFO Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. [11:8] read-only TX_CTRL0 Transmit Control Register 0. 0x24 TXPRELD Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. [0:0] normal Normal TX FIFO Operation. 0 preload TX FIFO Preload mode. 1 TXFSH Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. [7:7] not_flushed FIFO not flushed. 0 flush Flush TX_FIFO. 1 TXTH Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. [11:8] TX_CTRL1 Transmit Control Register 1. 0x28 TXRDY Transmit FIFO Preload Ready. [0:0] not_ready TX FIFO not ready to transmit preloaded data. 0 ready TX FIFO ready to transmit preloaded data. 1 TXLAST Slave mode transmit last. [1:1] pause_on_last Hold SCL low after transmitting the last character in the TX FIFO until more characters are loaded. 0 end_on_last Release SCL after transmitting the last character in the TXT FIFO. 1 TXFIFO Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. [11:8] read-only FIFO Data Register. 0x2C DATA Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. 0 8 MSTR_MODE Master Control Register. 0x30 START Setting this bit to 1 will start a master transfer. [0:0] start Start Master Mode transfer. 1 RESTART Setting this bit to 1 will generate a repeated START. [1:1] restart Send a repeated start bit. 1 STOP Setting this bit to 1 will generate a STOP condition. [2:2] stop Send a stop condition. 1 SEA Slave Extend Address Select. [7:7] 7BIT_ADDR 7-bit address. 0 10BIT_ADDR 10-bit address. 1 CLK_LO Clock Low Register. 0x34 SCL_LO Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. [8:0] CLK_HI Clock high Register. 0x38 SCL_HI Clock High. In master mode, these bits define the SCL high period. [8:0] TIMEOUT Timeout Register 0x40 TO SCL Timeout Period [15:0] SLV_ADDR Slave Address Register. 0x44 SLA Slave Address. [9:0] EA Slave Mode Extended Address Select. [15:15] 7BIT_ADDR 7-bit address. 0 10BIT_ADDR 10-bit address. 1 DMA DMA Register. 0x48 TXEN TX channel enable. [0:0] dis Disable. 0 en Enable. 1 RXEN RX channel enable. [1:1] dis Disable. 0 en Enable. 1 I2C1 Inter-Integrated Circuit. 1 0x4001E000 I2C1 I2C1 IRQ 36 ICC0 Instruction Cache Controller Registers 0x4002A000 0x00 0x1000 registers CACHE_ID Cache ID Register. 0x0000 read-only RELNUM Release Number. Identifies the RTL release version. 0 6 PARTNUM Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. 6 4 CCHID Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. 10 6 MEM_SIZE Memory Configuration Register. 0x0004 read-only 0x00080008 CCHSZ Cache Size. Indicates total size in Kbytes of cache. 0 16 MEMSZ Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. 16 16 CACHE_CTRL Cache Control and Status Register. 0x0100 ENABLE Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. 0 1 dis Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. 0 en Cache Enabled. 1 READY Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. 16 1 read-only notReady Not Ready. 0 ready Ready. 1 INVALIDATE Invalidate All Registers. 0x0700 read-write INVALID Invalidate. 0 32 OWM 1-Wire Master Interface. 0x4003D000 32 read-write 0 0x1000 registers OneWire 67 CFG 1-Wire Master Configuration. 0x0000 read-write long_line_mode Long Line Mode. [0:0] read-write force_pres_det Force Line During Presence Detect. [1:1] read-write bit_bang_en Bit Bang Enable. [2:2] read-write ext_pullup_mode Provide an extra output control to control an external pullup. [3:3] read-write ext_pullup_enable Enable External Pullup. [4:4] read-write single_bit_mode Enable Single Bit TX/RX Mode. [5:5] read-write overdrive Enables overdrive speed for 1-Wire operations. [6:6] read-write int_pullup_enable Enable intenral pullup. [7:7] read-write CLK_DIV_1US 1-Wire Master Clock Divisor. 0x0004 read-write DIVISOR Clock Divisor for 1Mhz. [7:0] read-write CTRL_STAT 1-Wire Master Control/Status. 0x0008 read-write start_ow_reset Start OW Reset. [0:0] read-write sra_mode SRA Mode. [1:1] read-write bit_bang_oe Bit Bang Output Enable. [2:2] read-write ow_input OW Input State. [3:3] read-only od_spec_mode Overdrive Spec Mode. [4:4] read-only presence_detect Presence Pulse Detected. [7:7] read-only DATA 1-Wire Master Data Buffer. 0x000C read-write tx_rx TX/RX Buffer. [7:0] read-write INTFL 1-Wire Master Interrupt Flags. 0x0010 read-write ow_reset_done OW Reset Sequence Completed. [0:0] read-write tx_data_empty TX Data Empty Interrupt Flag. [1:1] read-write rx_data_ready RX Data Ready Interrupt Flag [2:2] read-write line_short OW Line Short Detected Interrupt Flag. [3:3] read-write line_low OW Line Low Detected Interrupt Flag. [4:4] read-write INTEN 1-Wire Master Interrupt Enables. 0x0014 read-write ow_reset_done OW Reset Sequence Completed. [0:0] read-write oneToClear tx_data_empty Tx Data Empty Interrupt Enable. [1:1] read-write oneToClear rx_data_ready Rx Data Ready Interrupt Enable. [2:2] read-write oneToClear line_short OW Line Short Detected Interrupt Enable. [3:3] read-write oneToClear line_low OW Line Low Detected Interrupt Enable. [4:4] read-write oneToClear PT Pulse Train Pulse_Train 0x4003C020 32 read-write 0 0x0010 registers RATE_LENGTH Pulse Train Configuration 0x0000 read-write rate_control Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train. 0 27 read-write mode Pulse Train Output Mode/Train Length 27 5 read-write 32_BIT Pulse train, 32 bit pattern. 0 SQUARE_WAVE Square wave mode. 1 2_BIT Pulse train, 2 bit pattern. 2 3_BIT Pulse train, 3 bit pattern. 3 4_BIT Pulse train, 4 bit pattern. 4 5_BIT Pulse train, 5 bit pattern. 5 6_BIT Pulse train, 6 bit pattern. 6 7_BIT Pulse train, 7 bit pattern. 7 8_BIT Pulse train, 8 bit pattern. 8 9_BIT Pulse train, 9 bit pattern. 9 10_BIT Pulse train, 10 bit pattern. 10 11_BIT Pulse train, 11 bit pattern. 11 12_BIT Pulse train, 12 bit pattern. 12 13_BIT Pulse train, 13 bit pattern. 13 14_BIT Pulse train, 14 bit pattern. 14 15_BIT Pulse train, 15 bit pattern. 15 16_BIT Pulse train, 16 bit pattern. 16 17_BIT Pulse train, 17 bit pattern. 17 18_BIT Pulse train, 18 bit pattern. 18 19_BIT Pulse train, 19 bit pattern. 19 20_BIT Pulse train, 20 bit pattern. 20 21_BIT Pulse train, 21 bit pattern. 21 22_BIT Pulse train, 22 bit pattern. 22 23_BIT Pulse train, 23 bit pattern. 23 24_BIT Pulse train, 24 bit pattern. 24 25_BIT Pulse train, 25 bit pattern. 25 26_BIT Pulse train, 26 bit pattern. 26 27_BIT Pulse train, 27 bit pattern. 27 28_BIT Pulse train, 28 bit pattern. 28 29_BIT Pulse train, 29 bit pattern. 29 30_BIT Pulse train, 30 bit pattern. 30 31_BIT Pulse train, 31 bit pattern. 31 TRAIN Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length. 0x0004 read-write LOOP Pulse Train Loop Count 0x0008 read-write count Number of loops for this pulse train to repeat. 0 16 read-write delay Delay between loops of the Pulse Train in PT Peripheral Clock cycles 16 12 read-write RESTART Pulse Train Auto-Restart Configuration. 0x000C read-write pt_x_select Auto-Restart PT X Select 0 5 read-write on_pt_x_loop_exit Enable Auto-Restart on PT X Loop Exit 7 1 read-write pt_y_select Auto-Restart PT Y Select 8 5 read-write on_pt_y_loop_exit Enable Auto-Restart on PT Y Loop Exit 15 1 read-write PT1 Pulse Train 1 0x4003C030 PT2 Pulse Train 2 0x4003C040 PT3 Pulse Train 3 0x4003C050 PT4 Pulse Train 4 0x4003C060 PT5 Pulse Train 5 0x4003C070 PT6 Pulse Train 6 0x4003C080 PT7 Pulse Train 7 0x4003C090 PT8 Pulse Train 8 0x4003C0A0 PT9 Pulse Train 9 0x4003C0B0 PT10 Pulse Train 10 0x4003C0C0 PT11 Pulse Train 11 0x4003C0D0 PT12 Pulse Train 12 0x4003C0E0 PT13 Pulse Train 13 0x4003C0F0 PT14 Pulse Train 14 0x4003C1000 PT15 Pulse Train 15 0x4003C110 PTG Pulse Train Generation Pulse_Train 0x4003C000 32 read-write 0 0x0018 registers PT Pulse Train IRQ 59 ENABLE Global Enable/Disable Controls for All Pulse Trains 0x0000 read-write pt0 Enable/Disable control for PT0 0 1 read-write pt1 Enable/Disable control for PT1 1 1 read-write pt2 Enable/Disable control for PT2 2 1 read-write pt3 Enable/Disable control for PT3 3 1 read-write pt4 Enable/Disable control for PT4 4 1 read-write pt5 Enable/Disable control for PT5 5 1 read-write pt6 Enable/Disable control for PT6 6 1 read-write pt7 Enable/Disable control for PT7 7 1 read-write pt8 Enable/Disable control for PT8 8 1 read-write pt9 Enable/Disable control for PT9 9 1 read-write pt10 Enable/Disable control for PT10 10 1 read-write pt11 Enable/Disable control for PT11 11 1 read-write pt12 Enable/Disable control for PT12 12 1 read-write pt13 Enable/Disable control for PT13 13 1 read-write pt14 Enable/Disable control for PT14 14 1 read-write pt15 Enable/Disable control for PT15 15 1 read-write RESYNC Global Resync (All Pulse Trains) Control 0x0004 read-write pt0 Resync control for PT0 0 1 read-write pt1 Resync control for PT1 1 1 read-write pt2 Resync control for PT2 2 1 read-write pt3 Resync control for PT3 3 1 read-write pt4 Resync control for PT4 4 1 read-write pt5 Resync control for PT5 5 1 read-write pt6 Resync control for PT6 6 1 read-write pt7 Resync control for PT7 7 1 read-write pt8 Resync control for PT8 8 1 read-write pt9 Resync control for PT9 9 1 read-write pt10 Resync control for PT10 10 1 read-write pt11 Resync control for PT11 11 1 read-write pt12 Resync control for PT12 12 1 read-write pt13 Resync control for PT13 13 1 read-write pt14 Resync control for PT14 14 1 read-write pt15 Resync control for PT15 15 1 read-write INTFL Pulse Train Interrupt Flags 0x0008 read-write pt0 Pulse Train 0 Stopped Interrupt Flag 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Flag 1 1 read-write pt2 Pulse Train 2 Stopped Interrupt Flag 2 1 read-write pt3 Pulse Train 3 Stopped Interrupt Flag 3 1 read-write pt4 Pulse Train 4 Stopped Interrupt Flag 4 1 read-write pt5 Pulse Train 5 Stopped Interrupt Flag 5 1 read-write pt6 Pulse Train 6 Stopped Interrupt Flag 6 1 read-write pt7 Pulse Train 7 Stopped Interrupt Flag 7 1 read-write pt8 Pulse Train 8 Stopped Interrupt Flag 8 1 read-write pt9 Pulse Train 9 Stopped Interrupt Flag 9 1 read-write pt10 Pulse Train 10 Stopped Interrupt Flag 10 1 read-write pt11 Pulse Train 11 Stopped Interrupt Flag 11 1 read-write pt12 Pulse Train 12 Stopped Interrupt Flag 12 1 read-write pt13 Pulse Train 13 Stopped Interrupt Flag 13 1 read-write pt14 Pulse Train 14 Stopped Interrupt Flag 14 1 read-write pt15 Pulse Train 15 Stopped Interrupt Flag 15 1 read-write INTEN Pulse Train Interrupt Enable/Disable 0x000C read-write pt0 Pulse Train 0 Stopped Interrupt Enable/Disable 0 1 read-write pt1 Pulse Train 1 Stopped Interrupt Enable/Disable 1 1 read-write pt2 Pulse Train 2 Stopped Interrupt Enable/Disable 2 1 read-write pt3 Pulse Train 3 Stopped Interrupt Enable/Disable 3 1 read-write pt4 Pulse Train 4 Stopped Interrupt Enable/Disable 4 1 read-write pt5 Pulse Train 5 Stopped Interrupt Enable/Disable 5 1 read-write pt6 Pulse Train 6 Stopped Interrupt Enable/Disable 6 1 read-write pt7 Pulse Train 7 Stopped Interrupt Enable/Disable 7 1 read-write pt8 Pulse Train 8 Stopped Interrupt Enable/Disable 8 1 read-write pt9 Pulse Train 9 Stopped Interrupt Enable/Disable 9 1 read-write pt10 Pulse Train 10 Stopped Interrupt Enable/Disable 10 1 read-write pt11 Pulse Train 11 Stopped Interrupt Enable/Disable 11 1 read-write pt12 Pulse Train 12 Stopped Interrupt Enable/Disable 12 1 read-write pt13 Pulse Train 13 Stopped Interrupt Enable/Disable 13 1 read-write pt14 Pulse Train 14 Stopped Interrupt Enable/Disable 14 1 read-write pt15 Pulse Train 15 Stopped Interrupt Enable/Disable 15 1 read-write SAFE_EN Pulse Train Global Safe Enable. 0x0010 write-only PT0 0 1 write-only PT1 1 1 write-only PT2 2 1 write-only PT3 3 1 write-only PT4 4 1 write-only PT5 5 1 write-only PT6 6 1 write-only PT7 7 1 write-only PT8 8 1 write-only PT9 9 1 write-only PT10 10 1 write-only PT11 11 1 write-only PT12 12 1 write-only PT13 13 1 write-only PT14 14 1 write-only PT15 15 1 write-only SAFE_DIS Pulse Train Global Safe Disable. 0x0014 write-only PT0 0 1 write-only PT1 1 1 write-only PT2 2 1 write-only PT3 3 1 write-only PT4 4 1 write-only PT5 5 1 write-only PT6 6 1 write-only PT7 7 1 write-only PT8 8 1 write-only PT9 9 1 write-only PT10 10 1 write-only PT11 11 1 write-only PT12 12 1 write-only PT13 13 1 write-only PT14 14 1 write-only PT15 15 1 write-only PWRSEQ Power Sequencer / Low Power Control Register. 0x40006800 0x00 0x400 registers CTRL Low Power Control Register. 0x00 RAMRET System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 2 dis Disable Ram Retention. 0 en1 Enable System RAM 0 retention. 1 en2 Enable System RAM 0 and 1 retention. 2 en3 Enable System RAM 0 and 1 retention, if RREGEN=0, Enable all System RAM retention. 3 RREGEN Backup Mode RAM Retention Regulator Enable 8 1 dis Disabled. 0 en Enabled. 1 BKGRND Background Mode Enable. This bit allows low-power background mode operations, while the CPU is in DeepSleep. 9 1 dis Disabled. 0 en Enabled. 1 FWKM Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). 10 1 dis Disabled. 0 en Enabled. 1 BGOFF Bandgap OFF. This controls the System Bandgap in DeepSleep mode. 11 1 on Bandgap is always ON. 0 off Bandgap is OFF in DeepSleep mode(default). 1 PORVCOREMD VCORE POR Monitor for DEEPSLEEP and BACKUP Disable Write 1 to disable the power failure monitor. With the power failure monitor enabled, if the voltage drops below the trigger voltage the device enters a Power-On Reset. 12 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VCOREMD VDDC(Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. 20 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VRTCMD VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. 21 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDAMD VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 22 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDIOMD VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 23 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDIOHMD VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 24 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 PORVDDIOMD VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 25 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 PORVDDIOHMD VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. 26 1 en Enable if Bandgap is ON(default) 0 dis Disabled. 1 VDDBMD VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. 27 1 en Enabled. 0 dis Disabled. 1 GPIO0_WK_FL Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. 0x04 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 32 GPIO0_WK_EN Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x08 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 32 GPIO1_WK_FL Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 32 GPIO1_WK_EN Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 32 GPIO2_WK_FL Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO2. 0x14 WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 32 GPIO2_WK_EN Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. 0x18 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 32 GPIO3_WK_FL Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO3. 0x1C WAKEST Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. 0 10 GPIO3_WK_EN Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO3. 0x20 WAKEEN Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 10 USB_WK_FL Low Power Peripheral Wakeup Status Register. 0x30 USBLSWKST USB UTMI Linestate Detect Wakeup Flag(write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. 0 2 dplus D Plus line state change. 0 dminus D Minus line state change. 1 USBVBUSWKST USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. 2 1 normal Normal operation. 0 stchng Disabled. 1 USB_WK_EN Low Power Peripheral Wakeup Enable Register. 0x34 USBLSWKEN USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set. 0 2 dis Disable. 0 en Enabled. 3 USBVBUSWKEN USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. 2 1 dis Disable. 0 en Enabled. 1 MEM_PWR Low Power Memory Shutdown Control. 0x40 SRAM0SD System RAM block 0 Shut Down. 0 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM1SD System RAM block 1 Shut Down. 1 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM2SD System RAM block 2 Shut Down. 2 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM3SD System RAM block 3 Shut Down. 3 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM4SD System RAM block 4 Shut Down. 4 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM5SD System RAM block 5 Shut Down. 5 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SRAM6SD System RAM block 6 Shut Down. 6 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ICACHESD Instruction Cache RAM Shut Down. 7 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ICACHEXIPSD XiP Instruction Cache RAM Shut Down. 8 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 SCACHESD System Cache RAM Shut Down. 9 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 CRYPTOSD Crypto MAA RAM Shut Down. 10 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 USBFIFOSD USB FIFO Shut Down. 11 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 ROMSD ROM Shut Down. 12 1 normal Normal Operating Mode. 0 shutdown Shutdown Mode. 1 RTC Real Time Clock and Alarm. 0x40006000 0x00 0x400 registers RTC RTC interrupt. 3 SEC RTC Second Counter. This register contains the 32-bit second counter. 0x00 0x00000000 SEC RTC Seconds Counter. 0 32 SSEC RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. 0x04 0x00000000 SSEC RTC Sub-second Counter. 0 8 TODA Time-of-day Alarm. 0x08 0x00000000 TOD_ALARM Time-of-day Alarm. 0 20 SSECA RTC sub-second alarm. This register contains the reload value for the sub-second alarm. 0x0C 0x00000000 SSEC_ALARM This register contains the reload value for the sub-second alarm. 0 32 CTRL RTC Control Register. 0x10 0x00000008 0xFFFFFF38 ENABLE Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 dis Disable. 0 en Enable. 1 TOD_ALARM_EN Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 dis Disable. 0 en Enable. 1 SSEC_ALARM_EN Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 dis Disable. 0 en Enable. 1 BUSY RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 read-only idle Idle. 0 busy Busy. 1 READY RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 4 1 not_ready Register has not updated. 0 ready Ready. 1 READY_INT_EN RTC Ready Interrupt Enable. 5 1 dis Disable. 0 en Enable. 1 TOD_ALARM_FL Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 read-only inactive Not active 0 Pending Active 1 SSEC_ALARM_FL Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 read-only inactive Not active 0 Pending Active 1 SQWOUT_EN Square Wave Output Enable. 8 1 dis Disabled. 0 en Enabled. 1 FREQ_SEL Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. 9 2 freq1Hz 1 Hz (Compensated). 0 freq512Hz 512 Hz (Compensated). 1 freq4KHz 4 KHz. 2 ACRE Asynchronous Counter Read Enable. 14 1 sync SEC and SSEC registers synchronized and should only be accessed while CTRL.rdy = 1. 0 async SEC and SSEC registers are asynchronous and will require software interaction to ensure data accuracy. 1 WRITE_EN Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. 15 1 dis Writes to RTC_CTRL.enable are ignored. 0 en Writes to RTC_CTRL.enable are allowed. 1 OSCCTRL RTC Oscillator Control Register. 0x18 0x00000000 FILTER_EN Enables analog deglitch filter. 0 1 IBIAS_SEL If IBIAS_EN is 1, selects 4x,2x mode. 1 1 HYST_EN Enables high current hysteresis buffer. 2 1 IBIAS_EN Enables higher 4x,2x current modes. 3 1 BYPASS RTC Crystal Bypass 4 1 32KOUT RTC 32kHz Square Wave Output 5 1 SDHC SDHC/SDIO Controller 0x40037000 0 0x1000 registers SDHC 66 SDMA SDMA System Address / Argument 2. 0x00 32 ADDR SDMA System Address / Argument 2 of Auto CMD23. 0 32 BLK_SIZE Block Size. 0x04 16 TRANS Transfer Block Size. 0 12 HOST_BUF Host SDMA Buffer Boundary. 12 3 4KB 0 8KB 1 16KB 2 32KB 3 64KB 4 128KB 5 256KB 6 512KB 7 BLK_CNT Block Count. 0x06 16 COUNT Blocks Count For Current Transfer. 0 16 ARG_1 Argument 1. 0x08 32 CMD Command Argument 1. 0 32 TRANS Transfer Mode. 0x0C 16 DMA_EN DMA Enable. 0 1 dis 0 en 1 BLK_CNT_EN Block Count Enable. 1 1 dis 0 en 1 AUTO_CMD_EN Auto CMD Enable. 2 2 disable 0 cmd12 1 cmd23 2 READ_WRITE Data Transfer Direction Select. 4 1 write 0 read 1 MULTI Multi / Single Block Select. 5 1 multi 1 single 0 CMD Command. 0x0E 16 RESP_TYPE Response Type Select. 0 2 none 0 resp136 1 resp48 2 resp48_busy 3 CRC_CHK_EN Command CRC Check Enable. 3 1 en 1 dis 0 IDX_CHK_EN Command Index Check Enable. 4 1 en 1 dis 0 DATA_PRES_SEL Data Present Select. 5 1 TYPE Command Type. 6 2 normal 0 suspend 1 resume 2 abort 3 IDX Command Index. 8 6 8 2 RESP[%s] Response 0 Register 0-15. 0x010 16 CMD_RESP Command Response. 0 16 BUFFER Buffer Data Port. 0x20 32 DATA Buffer Data. 0 32 PRESENT Present State. 0x024 32 read-only CMD_COMP Command Inhibit (CMD). 0 1 read-only DAT Command Inhibit (DAT). 1 1 read-only DAT_LINE_ACTIVE DAT Line Active. 2 1 read-only RETUNING Re-Tuning Request. 3 1 read-only WRITE_TRANSFER Write Transfer Active. 8 1 read-only READ_TRANSFER Read Transfer Active. 9 1 read-only BUFFER_WRITE Buffer Write Enable. 10 1 read-only BUFFER_READ Buffer Read Enable. 11 1 read-only CARD_INSERTED Card Inserted. 16 1 read-only CARD_STATE Card State Stable. 17 1 read-only CARD_DETECT Card Detect Pin Level. 18 1 read-only WP Write Protect Switch Pin Level. 19 1 read-only DAT_SIGNAL_LEVEL DAT[3:0] Line Signal Level. 20 4 CMD_SIGNAL_LEVEL CMD Line Signal Level. 24 1 HOST_CN_1 Host Control 1. 0x028 8 LED_CN LED Control. 0 1 DATA_TRANSFER_WIDTH Data Transfer Width. 1 1 HS_EN High Speed Enable. 2 1 DMA_SELECT DMA Select. 3 2 EXT_DATA_TRANSFER_WIDTH Extended Data Transfer Width. 5 1 CARD_DETECT_TEST Card Detect Test Level. 6 1 CARD_DETECT_SIGNAL Card Detect Signal Selection. 7 1 PWR Power Control. 0x029 8 BUS_POWER SD Bus Power. 0 1 BUS_VOLT_SEL SD Bus Voltage Select. 1 3 1v8_typ 5 3v_typ 6 3v3_typ 7 BLK_GAP Block Gap Control. 0x02A 8 STOP Stop At Block Gap Request. 0 1 CONT Continue Request. 1 1 READ_WAIT Read Wait Control. 2 1 INTR Interrupt At Block Gap. 3 1 WAKEUP Wakeup Control. 0x02B 8 CARD_INT Wakeup Event Enable On Card Interrupt. 0 1 CARD_INS Wakeup Event Enable On SD Card Insertion. 1 1 CARD_REM Wakeup Event Enable On SD Card Removal. 2 1 CLK_CN Clock Control. 0x02C 16 INTERNAL_CLK_EN Internal Clock Enable. 0 1 INTERNAL_CLK_STABLE Internal Clock Stable. 1 1 read-only SD_CLK_EN SD Clock Enable. 2 1 CLK_GEN_SEL Clock Generator Select. 5 1 read-only UPPER_SDCLK_FREQ_SEL Upper Bits of SDCLK Frequency Select. 6 2 SDCLK_FREQ_SEL SDCLK Frequency Select. 8 8 TO Timeout Control. 0x02E 8 DATA_COUNT_VALUE Data Timeout Counter Value. 0 4 2POW13 0 2POW14 1 2POW15 2 2POW16 3 2POW17 4 2POW18 5 2POW19 6 2POW20 7 2POW21 8 2POW22 9 2POW23 10 2POW24 11 2POW25 12 2POW26 13 2POW27 14 SW_RESET Software Reset. 0x02F 8 RESET_ALL Software Reset For All. 0 1 RESET_CMD Software Reset For CMD Line. 1 1 RESET_DAT Software Reset For DAT Line. 2 1 INT_STAT Normal Interrupt Status. 0x030 16 CMD_COMP Command Complete. 0 1 TRANS_COMP Transfer Complete. 1 1 BLK_GAP_EVENT Block Gap Event. 2 1 DMA DMA Interrupt. 3 1 BUFF_WR_READY Buffer Write Ready. 4 1 BUFF_RD_READY Buffer Read Ready. 5 1 CARD_INSERTION Card Insertion. 6 1 CARD_REMOVAL Card Removal. 7 1 CARD_INTR Card Interrupt. 8 1 RETUNING Re-Tuning Event. 12 1 ERR_INTR Error Interrupt. 15 1 ER_INT_STAT Error Interrupt Status. 0x032 16 CMD_TO Command Timeout Error. 0 1 CMD_CRC Command CRC Error. 1 1 CMD_END_BIT Command End Bit Error. 2 1 CMD_IDX Command Index Error. 3 1 DATA_TO Data Timeout Error. 4 1 DATA_CRC Data CRC Error. 5 1 DATA_END_BIT Data End Bit Error. 6 1 CURRENT_LIMIT Current Limit Error. 7 1 AUTO_CMD_12 Auto CMD Error. 8 1 ADMA ADMA Error. 9 1 DMA DMA Error. 12 1 INT_EN Normal Interrupt Status Enable. 0x034 16 CMD_COMP Command Complete Status Enable. 0 1 TRANS_COMP Transfer Complete Status Enable. 1 1 BLK_GAP Block Gap Event Status Enable. 2 1 DMA DMA Interrupt Status Enable. 3 1 BUFFER_WR Buffer Write Ready Status Enable. 4 1 BUFFER_RD Buffer Read Ready Status Enable. 5 1 CARD_INSERT Card Insertion Status Enable. 6 1 CARD_REMOVAL Card Removal Status Enable. 7 1 CARD_INT Card Interrupt Status Enable. 8 1 RETUNING Re-Tuning Event Status Enable. 12 1 ER_INT_EN Error Interrupt Status Enable. 0x36 16 CMD_TO Command Timeout Error Status Enable. 0 1 CMD_CRC Command CRC Error Status Enable. 1 1 CMD_END_BIT Command End Bit Error Status Enable. 2 1 CMD_IDX Command Index Error Status Enable. 3 1 DATA_TO Data Timeout Error Status Enable. 4 1 DATA_CRC Data CRC Error Status Enable. 5 1 DATA_END_BIT Data End Bit Error Status Enable. 6 1 AUTO_CMD_12 Auto CMD Error Status Enable. 8 1 ADMA ADMA Error Status Enable. 9 1 TUNING Tuning Error Status Enable. 10 1 VENDOR Vendor Specific Error Status Enable. 12 1 INT_SIGNAL Normal Interrupt Signal Enable. 0x038 16 CMD_COMP Command Complete Signal Enable. 0 1 TRANS_COMP Transfer Complete Signal Enable. 1 1 BLK_GAP Block Gap Event Signal Enable. 2 1 DMA DMA Interrupt Signal Enable. 3 1 BUFFER_WR Buffer Write Ready Signal Enable. 4 1 BUFFER_RD Buffer Read Ready Signal Enable. 5 1 CARD_INSERT Card Insertion Signal Enable. 6 1 CARD_REMOVAL Card Removal Signal Enable. 7 1 CARD_INT Card Interrupt Signal Enable. 8 1 RETUNING Re-Tuning Event Signal Enable. 12 1 ER_INT_SIGNAL Error Interrupt Signal Enable. 0x03A 16 CMD_TO Command Timeout Error Signal Enable. 0 1 CMD_CRC Command CRC Error Signal Enable. 1 1 CMD_END_BIT Command End Bit Error Signal Enable. 2 1 CMD_IDX Command Index Error Signal Enable. 3 1 DATA_TO Data Timeout Error Signal Enable. 4 1 DATA_CRC Data CRC Error Signal Enable. 5 1 DATA_END_BIT Data End Bit Error Signal Enable. 6 1 CURRENT_LIMIT Current Limit Error Signal Enable. 7 1 AUTO_CMD_12 Auto CMD Error Signal Enable. 8 1 ADMA ADMA Error Signal Enable. 9 1 TUNING Tuning Error Signal Enable. 10 1 TAR_RESP Target Response Error Signal Enable. 12 1 AUTO_CMD_ER Auto CMD Error Status. 0x03C 16 NOT_EXCUTED Auto CMD12 Not Executed. 0 1 TO Auto CMD Timeout Error. 1 1 CRC Auto CMD CRC Error. 2 1 END_BIT Auto CMD End Bit Error. 3 1 INDEX Auto CMD Index Error. 4 1 NOT_ISSUED Command Not Issued By Auto CMD12 Error. 7 1 HOST_CN_2 Host Control 2. 0x03E 16 UHS UHS Mode Select. 0 3 sdr12 0 sdr25 1 sdr50 2 ddr50 4 1_8V_SIGNAL 1.8V Signaling Enable. 3 1 DRIVER_STRENGTH Driver Strength Select. 4 2 typeB 0 typeA 1 typeC 2 typrD 3 EXCUTE Execute Tuning. 6 1 SAMPLING_CLK Sampling Clock Select. 7 1 ASYNCH_INT Asynchronous Interrupt Enable. 14 1 PRESET_VAL_EN Preset Value Enable. 15 1 CFG_0 Capabilities 0-31. 0x040 32 read-only TO_FREQ Timeout Clock Frequency. 0 6 read-only 1mhz 1 CLK_UNIT Timeout Clock Unit. 7 1 read-only CLK_FREQ Base Clock Frequency For SD Clock. 8 8 read-only MAX_BLK_LEN Max Block Length. 16 2 read-only 2048_bytes 2 8_BIT 8-bit Support for Embedded Device. 18 1 read-only ADMA2 ADMA2 Support. 19 1 read-only HS High Speed Support. 21 1 read-only SDMA SDMA Support. 22 1 read-only SUSPEND Suspend/Resume Support. 23 1 read-only 3_3V Voltage Support 3.3V. 24 1 read-only 3_0V Voltage Support 3.0V. 25 1 read-only 1_8V Voltage Support 1.8V. 26 1 read-only 64_BIT_SYS_BUS 64-bit System Bus Support. 28 1 read-only ASYNC_INT Asynchronous Interrupt Support. 29 1 read-only SLOT_TYPE Slot Type. 30 2 read-only CFG_1 Capabilities 32-63. 0x044 32 read-only SDR50 SDR50 Support. 0 1 read-only SDR104 SDR104 Support. 1 0 read-only DDR50 DDR50 Support. 2 1 read-only DRIVER_A Driver Type A Support. 4 1 read-only DRIVER_C Driver Type C Support. 5 1 read-only DRIVER_D Driver Type D Support. 6 1 read-only TIMER_CNT_TUNING Timer Count for Re-Tuning. 8 4 read-only dis 0 1sec 1 2sec 2 4sec 3 8sec 4 16sec 5 32sec 6 64sec 7 128sec 8 256sec 9 512sec 10 1024sec 11 TUNING_SDR50 Use Tuning for SDR50. 13 1 read-only RETUNING Re-Tuning Modes. 14 2 read-only CLK_MULTI Clock Multiplier. 16 8 read-only MAX_CURR_CFG Maximum Current Capabilities. 0x048 32 read-only 3_3V Maximum Current for 3.3V. 0 8 read-only 3_0V Maximum Current for 3.0V. 8 8 read-only 1_8V Maximum Current for 1.8V. 16 8 read-only FORCE_CMD Force Event for Auto CMD Error Status. 0x050 16 write-only NOT_EXCU Force Event for Auto CMD12 Not Executed. 0 1 write-only TO Force Event for Auto CMD Timeout Error. 1 1 write-only CRC Force Event for Auto CMD CRC Error. 2 1 write-only END_BIT Force Event for Auto CMD End Bit Error. 3 1 write-only INDEX Force Event for Auto CMD Index Error. 4 1 write-only NOT_ISSUED Force Event for Command Not Issued By Auto CMD12 Error. 7 1 write-only FORCE_EVENT_INT_STAT Force Event for Error Interrupt Status. 0x052 16 CMD_TO Force Event for Command Timeout Error. 0 1 read-only CMD_CRC Force Event for Command CRC Error. 1 1 read-only CMD_END_BIT Force Event for Command End Bit Error. 2 1 read-only CMD_INDEX Force Event for Command Index Error. 3 1 read-only DATA_TO Force Event for Data Timeout Error. 4 1 read-only DATA_CRC Force Event for Data CRC Error. 5 1 read-only DATA_END_BIT Force Event for Data End Bit Error. 6 1 read-only CURR_LIMIT Force Event for Current Limit Error. 7 1 read-only AUTO_CMD Force Event for Auto CMD Error. 8 1 read-only ADMA Force Event for ADMA Error. 9 1 STAT_VENDOR Force Event for Vendor Specific Error Status. 12 4 write-only ADMA_ER ADMA Error Status. 0x054 8 STATE ADMA Error State. 0 2 LEN_MISMATCH ADMA Length Mismatch Error. 2 1 ADMA_ADDR_0 ADMA System Address 0-31. 0x058 32 ADDR ADMA System Address Part 1 (part 2 is ADMA_ADDR_1). 0 32 ADMA_ADDR_1 ADMA System Address 32-63. 0x05C 32 ADDR ADMA System Address Part 1 (part 2 is ADMA_ADDR_1). 0 32 PRESET_0 Preset Value for Initialization. 0x060 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only typeB 0 typeA 1 typeC 2 typeD 3 PRESET_1 Preset Value for Default Speed. 0x062 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only typeB 0 typeA 1 typeC 2 typeD 3 PRESET_2 Preset Value for High Speed. 0x064 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only typeB 0 typeA 1 typeC 2 typeD 3 PRESET_3 Preset Value for SDR12. 0x066 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only typeB 0 typeA 1 typeC 2 typeD 3 PRESET_4 Preset Value for SDR25. 0x068 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only typeB 0 typeA 1 typeC 2 typeD 3 PRESET_5 Preset Value for SDR50. 0x06A 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only typeB 0 typeA 1 typeC 2 typeD 3 PRESET_6 Preset Value for SDR104. 0x06C 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only typeB 0 typeA 1 typeC 2 typeD 3 PRESET_7 Preset Value for DDR50. 0x06E 16 read-only SDCLK_FREQ SDCLK Frequency Select Value. 0 10 read-only CLK_GEN Clock Generator Select Value. 10 1 read-only DRIVER_STRENGTH Driver Strength Select Value. 14 2 read-only typeB 0 typeA 1 typeC 2 typeD 3 SHARED_BUS SHARED_BUS. 0x0E0 32 SLOT_INT Slot Interrupt Status. 0x0FC 16 read-only INT_SIGNALS Interrupt Signal For Each Slot. 0 1 read-only HOST_CN_VER Host Controller Version. 0x0FE 16 SPEC_VER Specification Version Number. 0 8 VEND_VER Vendor Version Number. 8 8 SEMA The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. 0x4003E000 0x00 0x1000 registers 8 0x04 SEMAPHORES[%s] Read to test and set, returns prior value. Write 0 to clear semaphore. 0x000 32 sema 0 1 status Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. 0x100 32 STATUS 0 8 SMON The Security Monitor block used to monitor system threat conditions. 0x40004000 0x00 0x400 registers EXTSCN External Sensor Control Register. 0x00 0x3800FFC0 EXTS_EN0 External Sensor Enable for input/output pair 0. 0 1 dis Disable. 0 en Enable. 1 EXTS_EN1 External Sensor Enable for input/output pair 1. 1 1 dis Disable. 0 en Enable. 1 EXTS_EN2 External Sensor Enable for input/output pair 2. 2 1 dis Disable. 0 en Enable. 1 EXTS_EN3 External Sensor Enable for input/output pair 3. 3 1 dis Disable. 0 en Enable. 1 EXTS_EN4 External Sensor Enable for input/output pair 4. 4 1 dis Disable. 0 en Enable. 1 EXTS_EN5 External Sensor Enable for input/output pair 5. 5 1 dis Disable. 0 en Enable. 1 EXTCNT External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered. 16 5 EXTFRQ External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair. 21 3 freq2000Hz Div 4 (2000Hz). 0 freq1000Hz Div 8 (1000Hz). 1 freq500Hz Div 16 (500Hz). 2 freq250Hz Div 32 (250Hz). 3 freq125Hz Div 64 (125Hz). 4 freq63Hz Div 128 (63Hz). 5 freq31Hz Div 256 (31Hz). 6 RFU Reserved. Do not use. 7 DIVCLK Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor. 24 3 div1 Divide by 1 (8000 Hz). 0 div2 Divide by 2 (4000 Hz). 1 div4 Divide by 4 (2000 Hz). 2 div8 Divide by 8 (1000 Hz). 3 div16 Divide by 16 (500 Hz). 4 div32 Divide by 32 (250 Hz). 5 div64 Divide by 64 (125 Hz). 6 BUSY Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain. 30 1 read-only idle Idle. 0 busy Update in Progress. 1 LOCK Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. 31 1 unlocked Unlocked. 0 locked Locked. 1 INTSCN Internal Sensor Control Register. 0x04 0x7F00FFF7 SHIELD_EN Die Shield Enable. 0 1 dis Disable. 0 en Enable. 1 TEMP_EN Temperature Sensor Enable. 1 1 dis Disable. 0 en Enable. 1 VBAT_EN Battery Monitor Enable. 2 1 dis Disable. 0 en Enable. 1 LOTEMP_SEL Low Temperature Detection Select. 16 1 neg50C -50 degrees C. 0 neg30C -30 degrees C. 1 VCORELOEN VCORE Undervoltage Detect Enable. 18 1 dis Disable. 0 en Enable. 1 VCOREHIEN VCORE Overvoltage Detect Enable. 19 1 dis Disable. 0 en Enable. 1 VDDLOEN VDD Undervoltage Detect Enable. 20 1 dis Disable. 0 en Enable. 1 VDDHIEN VDD Overvoltage Detect Enable. 21 1 dis Disable. 0 en Enable. 1 VGLEN Voltage Glitch Detection Enable. 22 1 dis Disable. 0 en Enable. 1 LOCK Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. 31 1 unlocked Unlocked. 0 locked Locked. 1 SECALM Security Alarm Register. 0x08 0x00000000 0x00000000 DRS Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware. 0 1 complete No operation/complete. 0 start Start operation. 1 KEYWIPE Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped. 1 1 complete No operation/complete. 0 start Start operation. 1 SHIELDF Die Shield Flag. 2 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 LOTEMP Low Temperature Detect. 3 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 HITEMP High Temperature Detect. 4 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATLO Battery Undervoltage Detect. 5 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATHI Battery Overvoltage Detect. 6 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTF External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. 7 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VDDLO VDD Undervoltage Detect Flag. 8 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VCORELO VCORE Undervoltage Detect Flag. 9 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VCOREHI VCORE Overvoltage Detect Flag. 10 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VDDHI VDD Overvoltage Flag. 11 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 VGL Voltage Glitch Detection Flag. 12 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT0 External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 16 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT1 External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 17 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT2 External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 18 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT3 External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 19 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT4 External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 20 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT5 External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. 21 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN0 External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 24 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN1 External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 25 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN2 External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 26 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN3 External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 27 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN4 External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 28 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSWARN5 External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. 29 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 SECDIAG Security Diagnostic Register. 0x0C read-only 0x00000001 0xFFC0FE02 BORF Battery-On-Reset Flag. This bit is set once the back up battery is conneted. 0 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 SHIELDF Die Shield Flag. 2 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 LOTEMP Low Temperature Detect. 3 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 HITEMP High Temperature Detect. 4 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATLO Battery Undervoltage Detect. 5 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 BATHI Battery Overvoltage Detect. 6 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 DYNF Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. 7 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 AESKT AES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR. 8 1 incomplete Key has not been transferred. 0 complete Key has been transferred. 1 EXTSTAT0 External Sensor 0 Detect. 16 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT1 External Sensor 1 Detect. 17 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT2 External Sensor 2 Detect. 18 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT3 External Sensor 3 Detect. 19 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT4 External Sensor 4 Detect. 20 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 EXTSTAT5 External Sensor 5 Detect. 21 1 noEvent The event has not occurred. 0 occurred The event has occurred. 1 DLRTC DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred. 0x10 read-only 0x00000000 DLRTC DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured. 0 32 SECST Security Monitor Status 0x38 EXTSRS External Sensor Status. 0 1 allowed Allowed. 0 notallowed Not allowed. 1 INTSRS Internal Sensor Status. 1 1 allowed Allowed. 0 notallowed Not allowed. 1 SECALRS Securit Alarm Status. 2 1 allowed Allowed. 0 notallowed Not allowed. 1 SPI0 SPI peripheral. 0x40046000 0x00 0x1000 registers SPI0 16 FIFO32 Register for reading and writing the FIFO. 0x00 32 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 32 2 2 FIFO16[%s] Register for reading and writing the FIFO. FIFO32 0x00 16 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 16 4 1 FIFO8[%s] Register for reading and writing the FIFO. FIFO32 0x00 8 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 8 CTRL0 Register for controlling SPI peripheral. 0x04 read-write SPI_EN SPI Enable. 0 1 dis SPI is disabled. 0 en SPI is enabled. 1 MM_EN Master Mode Enable. 1 1 dis SPI is Slave mode. 0 en SPI is Master mode. 1 SS_IO Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 4 1 output Slave select 0 is output. 0 input Slave Select 0 is input, only valid if MMEN=1. 1 START Start Transmit. 5 1 start Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. 1 SS_CTRL Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. 8 1 deassert SPI De-asserts Slave Select at the end of a transaction. 0 assert SPI leaves Slave Select asserted at the end of a transaction. 1 SS_SEL Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 16 4 SS0 SS0 is selected. 0x1 SS1 SS1 is selected. 0x2 SS2 SS2 is selected. 0x4 SS3 SS3 is selected. 0x8 CTRL1 Register for controlling SPI peripheral. 0x08 read-write TX_NUM_CHAR Nubmer of Characters to transmit. 0 16 RX_NUM_CHAR Nubmer of Characters to receive. 16 16 CTRL2 Register for controlling SPI peripheral. 0x0C read-write CLK_PHA Clock Phase. 0 1 risingEdge Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 0 fallingEdge Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 1 CLK_POL Clock Polarity. 1 1 Normal Normal Clock. Use when in SPI Mode 0 and Mode 1 0 Inverted Inverted Clock. Use when in SPI Mode 2 and Mode 3 1 NUM_BITS Number of Bits per character. 8 4 16BITS 16 bits per character. 0 1BITS 1 bits per character. 1 2BITS 2 bits per character. 2 3BITS 3 bits per character. 3 4BITS 4 bits per character. 4 5BITS 5 bits per character. 5 6BITS 6 bits per character. 6 7BITS 7 bits per character. 7 8BITS 8 bits per character. 8 9BITS 9 bits per character. 9 10BITS 10 bits per character. 10 11BITS 11 bits per character. 11 12BITS 12 bits per character. 12 13BITS 13 bits per character. 13 14BITS 14 bits per character. 14 15BITS 15 bits per character. 15 BUS_WIDTH SPI Data width. 12 2 Mono 1 data pin. 0 Dual 2 data pins. 1 Quad 4 data pins. 2 THREE_WIRE Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 15 1 4wire Use four wire mode (Mono only). 0 3wire Use three wire mode. 1 SS_POL Slave Select Polarity, each Slave Select can have unique polarity. 16 8 SS0_high SS0 active high. 0x1 SS1_high SS1 active high. 0x2 SS2_high SS2 active high. 0x4 SS3_high SS3 active high. 0x8 SS_TIME Register for controlling SPI peripheral/Slave Select Timing. 0x10 read-write SSACT1 Slave Select Pre delay 1. 0 8 256 256 system clocks between SS active and first serial clock edge. 0 SSACT2 Slave Select Post delay 2. 8 8 256 256 system clocks between last serial clock edge and SS inactive. 0 SSINACT Slave Select Inactive delay. 16 8 256 256 system clocks between transactions. 0 CLK_CFG Register for controlling SPI clock rate. 0x14 read-write LO Low duty cycle control. In timer mode, reload[7:0]. 0 8 HI High duty cycle control. In timer mode, reload[15:8]. 8 8 SCALE System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. 16 4 DIV1 Divide SPI Clock Frequency by 1. 0 DIV2 Divide SPI Clock Frequency by 2. 1 DIV4 Divide SPI Clock Frequency by 4. 2 DIV8 Divide SPI Clock Frequency by 8. 3 DIV16 Divide SPI Clock Frequency by 16. 4 DIV32 Divide SPI Clock Frequency by 32. 5 DIV64 Divide SPI Clock Frequency by 64. 6 DIV128 Divide SPI Clock Frequency by 128. 7 DIV256 Divide SPI Clock Frequency by 256. 8 DMA Register for controlling DMA. 0x1C read-write TX_FIFO_LEVEL Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. 0 5 TX_FIFO_EN Transmit FIFO enabled for SPI transactions. 6 1 dis Transmit FIFO is not enabled. 0 en Transmit FIFO is enabled. 1 TX_FIFO_CLEAR Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 7 1 CLEAR Clear the Transmit FIFO, clears any pending TX FIFO status. 1 TX_FIFO_CNT Count of entries in TX FIFO. 8 6 read-only TX_DMA_EN TX DMA Enable. 15 1 dis TX DMA requests are disabled, andy pending DMA requests are cleared. 0 en TX DMA requests are enabled. 1 RX_FIFO_LEVEL Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. 16 5 RX_FIFO_EN Receive FIFO enabled for SPI transactions. 22 1 dis Receive FIFO is not enabled. 0 en Receive FIFO is enabled. 1 RX_FIFO_CLEAR Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 23 1 CLEAR Clear the Receive FIFO, clears any pending RX FIFO status. 1 RX_FIFO_CNT Count of entries in RX FIFO. 24 6 read-only RX_DMA_EN RX DMA Enable. 31 1 dis RX DMA requests are disabled, any pending DMA requests are cleared. 0 en RX DMA requests are enabled. 1 INT_FL Register for reading and clearing interrupt flags. All bits are write 1 to clear. 0x20 read-write TX_LEVEL TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EMPTY TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_LEVEL RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL RX FIFO FULL. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSA Slave Select Asserted. 4 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSD Slave Select Deasserted. 5 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 FAULT Multi-Master Mode Fault. 8 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 ABORT Slave Abort Detected. 9 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 M_DONE Master Done, set when SPI Master has completed any transactions. 11 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_OVR Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 12 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_UND Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. 13 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_OVR Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. 14 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_UND Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. 15 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 INT_EN Register for enabling interrupts. 0x24 read-write TX_LEVEL TX FIFO Threshold interrupt enable. 0 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_EMPTY TX FIFO Empty interrupt enable. 1 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_LEVEL RX FIFO Threshold Crossed interrupt enable. 2 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_FULL RX FIFO FULL interrupt enable. 3 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSA Slave Select Asserted interrupt enable. 4 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSD Slave Select Deasserted interrupt enable. 5 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 FAULT Multi-Master Mode Fault interrupt enable. 8 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 ABORT Slave Abort Detected interrupt enable. 9 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 M_DONE Master Done interrupt enable. 11 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_OVR Transmit FIFO Overrun interrupt enable. 12 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_UND Transmit FIFO Underrun interrupt enable. 13 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_OVR Receive FIFO Overrun interrupt enable. 14 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_UND Receive FIFO Underrun interrupt enable. 15 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 WAKE_FL Register for wake up flags. All bits in this register are write 1 to clear. 0x28 read-write TX_LEVEL Wake on TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EMPTY Wake on TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_LEVEL Wake on RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL Wake on RX FIFO Full. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 WAKE_EN Register for wake up enable. 0x2C read-write TX_LEVEL Wake on TX FIFO Threshold Crossed Enable. 0 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 TX_EMPTY Wake on TX FIFO Empty Enable. 1 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_LEVEL Wake on RX FIFO Threshold Crossed Enable. 2 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_FULL Wake on RX FIFO Full Enable. 3 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 STAT SPI Status register. 0x30 read-only BUSY SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 0 1 notActive SPI not active. 0 active SPI active. 1 SPI1 SPI peripheral. 1 0x40047000 SPI1 SPI1 IRQ 17 SPI2 SPI peripheral. 2 0x40048000 SPI2 SPI2 IRQ 18 SPI3 SPI peripheral. 3 0x400BE000 SPI3 SPI3 IRQ 56 SPIMSS Serial Peripheral Interface. SPIMSS 0x40018000 0x00 0x1000 registers DATA SPI 16-bit Data Access 0x00 read-write DATA SPI data. 0 16 CTRL SPI Control Register. 0x04 START SPI Enable. 0 1 stop 0 start 1 MMEN SPI Master Mode Enable. 1 1 slave 0 master 1 OD_OUT_EN Wired OR (open drain) Enable. 2 1 dis 0 en 1 CLKPOL Clock Polarity. 3 1 idleLo SCLK idles Low (0) after character transmission/reception. 0 idleHi SCLK idles High (1) after character transmission/reception. 1 PHASE Phase Select. 4 1 activeEdge Transmit on active edge of SCLK. 0 inactiveEdge Transmit on inactive edge of SCLK. 1 BIRQ Baud Rate Generator Timer Interrupt Request. 5 1 dis 0 en 1 STR Start SPI Interrupt. 6 1 complete No operation/complete. 0 start Start operation. 1 IRQE Interrupt Request Enable. 7 1 dis 0 en 1 INT_FL SPI Interrupt Flag Register. 0x08 0x00000001 SLAS Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning. 0 1 read-only selected 0 notSelected 1 TXST Transmit Status. 1 1 read-only idle 0 busy 1 TUND Transmit Underrun. 2 1 oneToClear noEvent The event has not occurred. 0 underrun The event has occurred. 1 ROVR Receive Overrun. 3 1 noEvent The event has not occurred. 0 overrun The event has occurred. 1 ABT Slave Mode Transaction Abort. 4 1 noEvent The event has not occurred. 0 aborted The event has occurred. 1 COL Collision. 5 1 noEvent The event has not occurred. 0 collision The event has occurred. 1 TOVR Transmit Overrun. 6 1 noEvent The event has not occurred. 0 overrun The event has occurred. 1 IRQ SPI Interrupt Request. 7 1 oneToClear inactive No interrupt is pending. 0 pending An interrupt is pending. 1 MOD SPI Mode Register. 0x0C SSV Slave Select Value. 0 1 lo The SSEL pin will be driven low. 0 hi The SSEL pin will be driven high. 1 SSEL Slave Select I/O. 1 1 input 0 output 1 NUMBITS 2 4 16bits 0 1bits 1 2bits 2 3bits 3 4bits 4 5bits 5 6bits 6 7bits 7 8bits 8 9bits 9 10bits 10 11bits 11 12bits 12 13bits 13 14bits 14 15bits 15 TX_ALIGN Transmit Left Justify. 7 1 lsb 0 msb 1 BRG Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4). 0x14 0x0000FFFF DIV Baud Rate Reload Value. 0 16 DMA SPI DMA Register. 0x18 0x00070007 TX_FIFO_LVL Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs. 0 3 1entries 0 2entries 1 3entries 2 4entries 3 5entries 4 6entries 5 7entries 6 8entries 7 TX_FIFO_CLR Transmit FIFO Clear. 4 1 write-only clear Start TX FIFO Clear operation. 1 TX_FIFO_CNT Transmit FIFO Count. 8 4 read-only TX_DMA_EN Transmit DMA Enable. 15 1 dis 0 en 1 RX_FIFO_LVL Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request. 16 3 fifo_level_enum 1entries 0 2entries 1 3entries 2 4entries 3 5entries 4 6entries 5 7entries 6 8entries 7 RX_FIFO_CLR Receive FIFO Clear. 20 1 clear Start RX FIFO clear operation. 1 RX_FIFO_CNT Receive FIFO Count. 24 4 read-only RX_DMA_EN Receive DMA Enable. 31 1 dis 0 en 1 I2S_CTRL I2S Control Register. 0x1C I2S_EN I2S Mode Enable. 0 1 dis 0 en 1 I2S_MUTE I2S Mute transmit. 1 1 normal Normal Transmit. 0 muted Transmit data is replaced with 0. 1 I2S_PAUSE I2S Pause transmit/receive. 2 1 normal Normal Transmit. 0 pause Halt transmit and receive FIFO and DMA access, transmit 0's. 1 I2S_MONO I2S Monophonic Audio Mode. 3 1 stereo Stereophonic audio. 0 mono Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored. 1 I2S_LJ I2S Left Justify. 4 1 lag Normal I2S audio protocol. 0 syncronized Audio data is synchronized with SSEL. 1 SPIXR SPIXR peripheral. 0x4003A000 0x00 0x1000 registers DATA32 Register for reading and writing the FIFO. 0x00 32 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 32 2 2 DATA16[%s] Register for reading and writing the FIFO. DATA32 0x00 16 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 16 4 1 DATA8[%s] Register for reading and writing the FIFO. DATA32 0x00 8 read-write DATA Read to pull from RX FIFO, write to put into TX FIFO. 0 8 ctrl1 Register for controlling SPI peripheral. 0x04 read-write ENABLE SPI Enable. 0 1 dis SPI is disabled. 0 en SPI is enabled. 1 MASTER Master Mode Enable. 1 1 dis SPI is Slave mode. 0 en SPI is Master mode. 1 SS_IO Slave Select 0, IO direction, to support Multi-Master mode, Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. 4 1 output Slave select 0 is output. 0 input Slave Select 0 is input, only valid if MMEN=1. 1 START Start Transmit. 5 1 start Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction completes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. 1 SS_CTRL Slave Select Control. 8 1 deassert SPI de-asserts Slave Select at the end of a transaction. 0 assert SPI leaves Slave Select asserted at the end of a transaction. 1 SS Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. 16 1 ctrl2 Register for controlling SPI peripheral. 0x08 read-write TX_NUM_CHAR Nubmer of Characters to transmit. 0 16 RX_NUM_CHAR Nubmer of Characters to receive. 16 16 ctrl3 Register for controlling SPI peripheral. 0x0C read-write CPHA Clock Phase. 0 1 risingEdge Data sampled on rising edge. 0 fallingEdge Data sample on falling edge. 1 CPOL Clock Polarity. 1 1 normal Normal clock. 0 inverted Inverted clock. 1 SCLK_INV Invert SCLK Feedback in Master Mode. 4 1 Normal SCLK is not inverted to Line Receiver. 0 NUMBITS Number of Bits per character. 8 4 16BITS 16 bits per character. 0 1BITS 1 bits per character. 1 2BITS 2 bits per character. 2 3BITS 3 bits per character. 3 4BITS 4 bits per character. 4 5BITS 5 bits per character. 5 6BITS 6 bits per character. 6 7BITS 7 bits per character. 7 8BITS 8 bits per character. 8 9BITS 9 bits per character. 9 10BITS 10 bits per character. 10 11BITS 11 bits per character. 11 12BITS 12 bits per character. 12 13BITS 13 bits per character. 13 14BITS 14 bits per character. 14 15BITS 15 bits per character. 15 DATA_WIDTH SPI Data width. 12 2 Mono 1 data pin. 0 Dual 2 data pins. 1 Quad 4 data pins. 2 THREE_WIRE Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. 15 1 4wire Use four wire mode (Mono only). 0 3wire Use three wire mode. 1 SSPOL Slave Select Polarity 16 1 activeLow Slave select is active low. 0 activeHigh Slave select is active high. 1 SS_TIME Register for controlling SPI peripheral. 0x10 read-write SSACT1 Slave Select Action delay 1. 0 8 SSACT2 Slave Select Action delay 2. 8 8 SSINACT Slave Select Inactive delay. 16 8 BRG_CTRL Register for controlling SPI clock rate. 0x14 read-write LO Low duty cycle control. In timer mode, reload[7:0]. 0 8 HI High duty cycle control. In timer mode, reload[15:8]. 8 8 SCALE System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. 16 4 div1 clk_freq = f_pclk/1. 0 div2 clk_freq = f_pclk/2. 1 div4 clk_freq = f_pclk/4. 2 div8 clk_freq = f_pclk/8. 3 div16 clk_freq = f_pclk/16. 4 div32 clk_freq = f_pclk/32. 5 div64 clk_freq = f_pclk/64. 6 div128 clk_freq = f_pclk/128. 7 div256 clk_freq = f_pclk/256. 8 DMA Register for controlling DMA. 0x1C read-write TX_FIFO_LEVEL Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. 0 5 TX_FIFO_EN Transmit FIFO enabled for SPI transactions. 6 1 dis Transmit FIFO is not enabled. 0 en Transmit FIFO is enabled. 1 TX_FIFO_CLEAR Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 7 1 clear Clear the Transmit FIFO, clears any pending TX FIFO status. 1 TX_FIFO_CNT Count of entries in TX FIFO. 8 6 TX_DMA_EN TX DMA Enable. 15 1 dis TX DMA requests are disabled, andy pending DMA requests are cleared. 0 en TX DMA requests are enabled. 1 RX_FIFO_LEVEL Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. 16 5 RX_FIFO_EN Receive FIFO enabled for SPI transactions. 22 1 dis Receive FIFO is not enabled. 0 en Receive FIFO is enabled. 1 RX_FIFO_CLEAR Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. 23 1 clear Clear the Receive FIFIO, clears any pending RX FIFO status. 1 RX_FIFO_CNT Count of entries in RX FIFO. 24 6 RX_DMA_EN RX DMA Enable. 31 1 dis RX DMA requests are disabled, any pending DMA requests are cleared. 0 en RX DMA requests are enabled. 1 int_fl Register for reading and clearing interrupt flags. All bits are write 1 to clear. 0x20 read-write TX_LEVEL TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EMPTY TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_LEVEL RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL RX FIFO FULL. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSA Slave Select Asserted. 4 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 SSD Slave Select Deasserted. 5 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 FAULT Multi-Master Mode Fault. 8 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 ABORT Slave Abort Detected. 9 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 M_DONE Master Done, set when SPI Master has completed any transactions. 11 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_OVR Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. 12 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_UND Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. 13 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_OVR Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. 14 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_UND Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. 15 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 int_en Register for enabling interrupts. 0x24 read-write TX_LEVEL TX FIFO Threshold interrupt enable. 0 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_EMPTY TX FIFO Empty interrupt enable. 1 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_LEVEL RX FIFO Threshold Crossed interrupt enable. 2 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_FULL RX FIFO FULL interrupt enable. 3 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSA Slave Select Asserted interrupt enable. 4 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 SSD Slave Select Deasserted interrupt enable. 5 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 FAULT Multi-Master Mode Fault interrupt enable. 8 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 ABORT Slave Abort Detected interrupt enable. 9 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 M_DONE Master Done interrupt enable. 11 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_OVR Transmit FIFO Overrun interrupt enable. 12 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 TX_UND Transmit FIFO Underrun interrupt enable. 13 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_OVR Receive FIFO Overrun interrupt enable. 14 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 RX_UND Receive FIFO Underrun interrupt enable. 15 1 dis Interrupt is disabled. 0 en Interrupt is enabled. 1 WAKE_FL Register for wake up flags. All bits in this register are write 1 to clear. 0x28 read-write TX_LEVEL Wake on TX FIFO Threshold Crossed. 0 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 TX_EMPTY Wake on TX FIFO Empty. 1 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_LEVEL Wake on RX FIFO Threshold Crossed. 2 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 RX_FULL Wake on RX FIFO Full. 3 1 clear Flag is set when value read is 1. Write 1 to clear this flag. 1 WAKE_EN Register for wake up enable. 0x2C read-write TX_LEVEL Wake on TX FIFO Threshold Crossed Enable. 0 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 TX_EMPTY Wake on TX FIFO Empty Enable. 1 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_LEVEL Wake on RX FIFO Threshold Crossed Enable. 2 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 RX_FULL Wake on RX FIFO Full Enable. 3 1 dis Wakeup source disabled. 0 en Wakeup source enabled. 1 STAT SPI Status register. 0x30 read-only BUSY SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 0 1 notActive SPI not active. 0 active SPI active. 1 XMEM_CTRL Register to control external memory. 0x34 read-write XMEM_RD_CMD Read command. 0 8 XMEM_WR_CMD Write command. 8 8 XMEM_DCLKS Dummy clocks. 16 8 XMEM_EN XMEM enable. 31 1 dis External memory disabled. 0 en External memory enabled. 1 SPIXFC SPI XiP Flash Configuration Controller 0x40027000 0 0x1000 registers SPIXFC SPIXFC IRQ 38 CFG Configuration Register. 0x00 SSEL Slaves Select. 0 3 slave0 Slave 0 is selected. 0 MODE Defines SPI Mode, Only valid values are 0 and 3. 4 2 mode0 SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0. 0 mode3 SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1. 3 PGSZ Page Size. 6 2 4bytes 4 bytes. 0 8bytes 8 bytes. 1 16bytes 16 bytes. 2 32bytes 32 bytes. 3 HICLK SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high. 8 4 16CLK 16 system clocks. 0 1CLK 1 system clocks. 1 2CLK 2 system clocks. 2 3CLK 3 system clocks. 3 4CLK 4 system clocks. 4 5CLK 5 system clocks. 5 6CLK 6 system clocks. 6 7CLK 7 system clocks. 7 8CLK 8 system clocks. 8 9CLK 9 system clocks. 9 10CLK 10 system clocks. 10 11CLK 11 system clocks. 11 12CLK 12 system clocks. 12 13CLK 13 system clocks. 13 14CLK 14 system clocks. 14 15CLK 15 system clocks. 15 LOCLK SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low. 12 4 16CLK 16 system clocks. 0 1CLK 1 system clocks. 1 2CLK 2 system clocks. 2 3CLK 3 system clocks. 3 4CLK 4 system clocks. 4 5CLK 5 system clocks. 5 6CLK 6 system clocks. 6 7CLK 7 system clocks. 7 8CLK 8 system clocks. 8 9CLK 9 system clocks. 9 10CLK 10 system clocks. 10 11CLK 11 system clocks. 11 12CLK 12 system clocks. 12 13CLK 13 system clocks. 13 14CLK 14 system clocks. 14 15CLK 15 system clocks. 15 SSACT Slaves Select Activate Timing. 16 2 0CLK 0 sytem clocks. 0 2CLK 2 sytem clocks. 1 4CLK 4 sytem clocks. 2 8CLK 8 sytem clocks. 3 INACT Slaves Select Inactive Timing. 18 2 4CLK 4 sytem clocks. 0 6CLK 6 sytem clocks. 1 8CLK 8 sytem clocks. 2 12CLK 12 sytem clocks. 3 IOSMPL Sample Delay 20 4 NODLY No sample clock delay. 0 1CLK 1 system clocks. 1 2CLK 2 system clocks. 2 3CLK 3 system clocks. 3 4CLK 4 system clocks. 4 5CLK 5 system clocks. 5 6CLK 6 system clocks. 6 7CLK 7 system clocks. 7 8CLK 8 system clocks. 8 9CLK 9 system clocks. 9 10CLK 10 system clocks. 10 11CLK 11 system clocks. 11 12CLK 12 system clocks. 12 13CLK 13 system clocks. 13 14CLK 14 system clocks. 14 15CLK 15 system clocks. 15 SS_POL SPIX Controller Slave Select Polarity Register. 0x04 SSPOL_0 Slave Select Polarity. 0 1 activeLo Active Low. 0 activeHi Active High. 1 GEN_CTRL SPIX Controller General Controller Register. 0x08 ENABLE SPI Master enable. 0 1 dis Disable SPI Master, putting a reset state. 0 en Enable SPI Master for processing transactions. 1 TFIFOEN Transaction FIFO Enable. 1 1 dis Disable Transaction FIFO. 0 en Enable Transaction FIFO. 1 RFIFOEN Result FIFO Enable. 2 1 dis Disable Result FIFO. 0 en Enable Result FIFO. 1 BBMODE Bit-Bang Mode. 3 1 dis Disable Bit-Bang Mode. 0 en Enable Bit-Bang Mode. 1 SSDR This bits reflects the state of the currently selected slave select. 4 1 output0 Selected Slave select output = 0. 0 output1 Selected Slave select output = 1. 1 SCKDR SSCLK Drive and State. 6 1 sck0 SCLK is 0. 0 sck1 SCLK is 1. 1 SDATAIN SDIO Input Data Value. 8 4 SDIO0 SDIO[0] 1 SDIO1 SDIO[1] 2 SDIO2 SDIO[2] 4 SDIO3 SDIO[3] 8 BBDAT No description available. 12 4 SDIO0 SDIO[0] 1 SDIO1 SDIO[1] 2 SDIO2 SDIO[2] 4 SDIO3 SDIO[3] 8 BBDATOEN Bit Bang SDIO Output Enable. 16 4 SDIO0 SDIO[0] 1 SDIO1 SDIO[1] 2 SDIO2 SDIO[2] 4 SDIO3 SDIO[3] 8 SIMPLE Simple Mode Enable. 20 1 dis Disable Simple Mode. 0 en Enable Simple Mode. 1 SIMPLERX Simple Receive Enable. 21 1 initSPI Initiate SPI transaction. 1 SMPLSS Simple Mode Slave Select. 22 1 deassertSS Deassert Slave select when SIMPLE = 1. 1 SCKFB Enable SCLK Feedback Mode. 24 1 dis 0 en 1 SCKFBINV SCK Invert. 25 1 normal 0 invert 1 FIFO_CTRL SPIX Controller FIFO Control and Status Register. 0x0C TFIFOLVL Transaction FIFO Almost Empty Level. 0 4 TFIFOCNT Transaction FIFO Used. 8 5 RFIFOLVL Results FIFO Almost Full Level. 16 5 RFIFOCNT Result FIFO Used. 24 6 SP_CTRL SPIX Controller Special Control Register. 0x10 SAMPL Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the next slave select assertion. 0 1 dis Disable sample mode. 0 en Enable sample mode. 1 SDIO_OUT SDIO Output Value Sample Mode 4 4 SDIO0 SDIO[0] 0x1 SDIO1 SDIO[1] 0x2 SDIO2 SDIO[2] 0x4 SDIO3 SDIO[3] 0x8 SDIO_OUT_EN SDIO Output Enable Sample Mode 8 4 SDIO0 SDIO[0] 0x1 SDIO1 SDIO[1] 0x2 SDIO2 SDIO[2] 0x4 SDIO3 SDIO[3] 0x8 SCKINH3 SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams. 16 1 en Allow trailing SCLK low pulse prior to Slave Select de-assertion. 0 dis Inhibit trailing SCLK low pulse prior to Slave Select de-assertion. 1 INT_FL SPIX Controller Interrupt Status Register. 0x14 TSTALL Transaction Stalled Interrupt Flag. 0 1 clear Clear interrupt. 1 RSTALL Results Stalled Interrupt Flag. 1 1 clear Clear interrupt. 1 TRDY Transaction Ready Interrupt Status. 2 1 clear Clear interrupt. 1 RDONE Results Done Interrupt Status. 3 1 clear Clear interrupt. 1 TFIFOAE Transaction FIFO Almost Empty Flag. 4 1 clear Clear interrupt. 1 RFIFOAF Results FIFO Almost Full Flag. 5 1 clear Clear interrupt. 1 INT_EN SPIX Controller Interrupt Enable Register. 0x18 TSTALLIE Transaction Stalled Interrupt Enable. 0 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 RSTALLIE Results Stalled Interrupt Enable. 1 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 TRDYIE Transaction Ready Interrupt Enable. 2 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 RDONEIE Results Done Interrupt Enable. 3 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 TFIFOAEIE Transaction FIFO Almost Empty Interrupt Enable. 4 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 RFIFOAFIE Results FIFO Almost Full Interrupt Enable. 5 1 dis Disable Interrupt. 0 en Enable Interrupt. 1 SPIXFC_FIFO SPI XiP Master Controller FIFO. 0x400BC000 0 0x1000 registers TX_8 SPI TX FIFO 8-Bit Write 0x00 8 uint8_t TX_16 SPI TX FIFO 16-Bit Write TX_8 0x00 16 uint16_t TX_32 SPI TX FIFO 32-Bit Write TX_8 0x00 32 uint32_t RX_8 SPI RX FIFO 8-Bit Access 0x04 8 uint8_t RX_16 SPI RX FIFO 16-Bit Access RX_8 0x04 16 uint16_t RX_32 SPI RX FIFO 32-Bit Access RX_8 0x04 32 uint32_t SPIXF SPIXF Master 0x40026000 0x00 0x1000 registers CFG SPIX Configuration Register. 0x00 MODE Defines SPI Mode, Only valid values are 0 and 3. 0 2 mode0 Description not available. 0 mode3 Description not available. 3 SSPOL Slave Select Polarity. 2 1 activeHi Slave Select is Active High. 0 activeLo Slave Select is Active Low. 1 SSEL Slave Select. Only valid value is zero. 4 3 slave0 Select slave 0. 0 LOCLK Number of system clocks that SCLK will be low when SCLK pulses are generated. 8 4 HICLK Number of system clocks that SCLK will be high when SCLK pulses are generated. 12 4 SSACT Slave Select Active Timing. 16 2 off 0 system clocks. 0 2clk 2 System clocks. 1 4clk 4 System clocks. 2 8clk 8 System clocks. 3 SSIACT Slave Select Inactive Timing. 18 2 1clk 1 system clocks. 0 3clk 3 System clocks. 1 5clk 5 System clocks. 2 9clk 9 System clocks. 3 FETCH_CTRL SPIX Fetch Control Register. 0x04 CMDVAL Command Value sent to target to initiate fetching from SPI flash. 0 8 CMDWTH Command Width. Number of data I/O used to send commands. 8 2 mono Single SDIO. 0 dual Dual SDIO. 1 quad Quad SDIO. 2 invalid Invalid. 3 ADDR_WIDTH Address Width. Number of data I/O used to send address, and mode/dummy clocks. 10 2 single Single SDIO. 0 dual Dual SDIO. 1 quad Quad SDIO. 2 invalid Invalid. 3 DATA_WIDTH Data Width. Number of data I/O used to receive data. 12 2 single Single SDIO. 0 dual Dual SDIO. 1 quad Quad SDIO. 2 invalid Invalid. 3 ADDR4 Four Byte Address Mode. Enables 4-byte Flash Address Mode. 16 1 3byte 3 Byte Address Mode. 0 4byte 4 Byte Address Mode. 1 MODE_CTRL SPIX Mode Control Register. 0x08 MDCLK Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch. 0 4 NOCMD No Command Mode. 8 1 always Send read command every time SPI transaction is initiated. 0 once Send read command only once. NO read command in subsequent SPI transactions. 1 MODE_SEND Mode Send. 9 1 next Send mode byte on next transaction. 1 MODE_DATA SPIX Mode Data Register. 0x0C MDDATA Mode Data. Specifies the data to send with the Dummy/Mode clocks. 0 16 MDOE Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA. 16 16 FB_CTRL SPIX Feedback Control Register. 0x10 FBMD Enable SCLK feedback mode. 0 1 dis Disable SCLK feedback mode. 0 en Enable SCLK feedback mode. 1 FBINV Invert SCLK in feedback mode. 1 1 dis Disable Invert SCLK feedback mode. 0 en Enable Invert SCLK feedback mode. 1 IO_CTRL SPIX IO Control Register. 0x1C SCK_DS SCLK drive Strength. This bit controls the drive strength on the SCLK pin. 0 1 Low Low drive strength. 0 High High drive strength. 1 SS_DS Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin. 1 1 Low Low drive strength. 0 High High drive strength. 1 SDIO_DS SDIO Drive Strength. This bit controls the drive strength of all SDIO pins. 2 1 Low Low drive strength. 0 High High drive strength. 1 PUPDCTRL IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins. 3 2 tri_state Tristate. 0 Pull_Up Pull-Up. 1 Pull_down Pull-Down. 2 SEC_CTRL SPIX Memory Security Control Register. 0x20 DEC_EN Decryption Enable. 0 1 dis Disable decryption of SPIX data. 0 en Enable decryption of SPIX data. 1 AUTH_DISABLE Integrity Enable. 1 1 en Integrity checking enabled. 0 dis Integrity checking disabled. 1 BUS_IDLE Bus Idle 0x24 BUSIDLE A 16-bit timer will be triggered for each external access. The timer will be restarted if another access is performed before the timer expires. When the timer expires, slave select will be deactivated. 0 16 BBFC Battery Backed Function Control Register. 0x40058000 0x00 0x400 registers BBFCR0 Register 0. 0x00 read-write CKPDRV Hyperbus CK Drive Setting. 0 4 CKNPDRV Hyperbus CKN Drive Setting. 4 4 RDSDLLEN Hyperbus RDS DLL Enable. 8 1 dis 0 en 1 NBBFC Non Battery-Backed Function Control Register. 0x40000800 0x00 0x400 registers REG0 Register 0. 0x00 read-write RDSGCSEL Hyperbus RDS Gray Code Select. 0 6 RDSGCSET Hyperbus RDS Set. 6 1 internal Select internal setting. 0 gray_code Select gray code. 1 HYPCGDLY Hyperbus Clock Generator Delay. 8 6 USBRCKSEL USB Reference Clock Select. 16 1 sys Generated clock from system clock. 0 dig Digital clock from a GPIO. 1 QSPI0SEL QSPI0 Function Select. 17 1 med Select SPI Medical functions. 0 qspi0 Select QSPI0 function. 1 I2C0DGEN0 I2C0 SDA Glitch Filter Enable. 20 1 dis Filter disabled. 0 en Filter enabled. 1 I2C0DGEN1 I2C0 SCL Glitch Filter Enable. 21 1 dis Filter disabled. 0 en Filter enabled. 1 I2C1DGEN0 I2C1 SDA Glitch Filter Enable. 22 1 dis Filter disabled. 0 en Filter enabled. 1 I2C1DGEN1 I2C1 SCL Glitch Filter Enable. 23 1 dis Filter disabled. 0 en Filter enabled. 1 REG1 Register 1. 0x04 read-write ACEN Auto-calibration Enable. 0 1 dis Disabled. 0 en Enabled. 1 ACRUN Autocalibration Run. 1 1 not Not Running. 0 run Running. 1 LDTRM Load Trim. 2 1 GAININV Invert Gain. 3 1 not Not Running. 0 run Running. 1 ATOMIC Atomic mode. 4 1 not Not Running. 0 run Running. 1 MU MU value. 8 12 REG2 Register 2. 0x08 read-write INTTRIM Initial Trim Setting. 0 9 MINTRM Minimum Trim Setting. 10 9 MAXTRM Maximum Trim Setting. 20 9 REG3 Register 3. 0x0C read-write DONECNT Automatic Calibration Done Counter Setting. 0 8 GCR Global Control Registers. 0x40000000 0 0x400 registers SCON System Control. 0x00 0xFFFFFFFE BSTAPEN Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. 0 1 dis Boundary Scan TAP port disabled. 0 en Boundary Scan TAP port enabled. 1 FLASH_PAGE_FLIP Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. 4 1 normal Physical layout matches logical layout. 0 flipped Bottom half mapped to logical top half and vice versa. 1 CCACHE_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 6 1 normal Normal Code Cache Operation 0 flush Code Caches and CPU instruction buffer are flushed 1 DCACHE_FLUSH Write 1 to flush the external memory controller's 16KB cache. This bit is automatically cleared to 0 when the flush is complete. 7 1 normal Normal External Cache Operation 0 flush External cache being flushed. 1 DCACHE_DIS Disable EMCC used for SPIXR or HyperBus/Xccela Bus code and data cache. 9 1 enabled EMCC enabled. 0 disabled EMCC disabled and line buffer bypassed. 1 CCHK Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 complete No operation/complete. 0 start Start operation. 1 CHKRES ROM Checksum Result. This bit is only valid when CHKRD=1. 15 1 pass ROM Checksum Correct. 0 fail ROM Checksum Fail. 1 OVR These bits select the operating voltage range. 16 2 0v9 0.9V +/- 10%. 0 1V 1.0V +/- 10%. 1 1V1 1.1V +/- 10%. 2 RST0 Reset. 0x04 DMA DMA Reset. 0 1 WDT0 Watchdog Timer Reset. 1 1 GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 GPIO1 GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. 3 1 GPIO2 GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states. 4 1 TIMER0 Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 TIMER1 Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 TIMER2 Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 TIMER3 Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 TIMER4 Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. 9 1 TIMER5 Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. 10 1 UART0 UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 UART1 UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. 12 1 SPI0 SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 SPI1 SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. 14 1 SPI2 SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. 15 1 I2C0 I2C0 Reset. 16 1 RTC RTC Reset. 17 1 TPU Trust Protection Unit Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block. 18 1 HBC HyperBus/Xccela controller reset. 21 1 TFT TFT controller reset. 22 1 USB USB Reset. 23 1 ADC Analog to Digital converter reset. 26 1 UART2 UART 2 reset. 28 1 SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 1 CLK_CTRL Clock Control. 0x08 0x00000008 SYSCLK_PRESCALE Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. 6 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 SYSOSC_SEL Clock Source Select. This 3 bit field selects the source for the system clock. 9 3 CRYPTO Internal Primary Oscilatior Clock 0 HFXIN 24MHz Internal Oscillator is used for the system clock. 2 NANORING 8kHz Internal Nano Ring Oscillator is used for the system clock. 3 HIRC96 120 MHz Internal Oscillator. 4 HIRC8 Internal 7.3728MHz oscillator. 5 X32K External 32KHz oscillator. 6 SYSOSC_RDY Clock Ready. This read only bit reflects whether the currently selected system clock source is running. 13 1 read-only busy Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 ready System clock running from CLKSEL clock source. 1 CCD Cryptographic clock divider 15 1 read-only non_div The cryptographic accelerator clock is running in non-divided mode. 0 div The cryptographic accelerator clock is running in divided mode. 1 X32K_EN 32KHz External Clock Enable. 17 1 CRYPTO_EN 50MHz High Frequency Internal Reference Clock Enable. 18 1 HIRC96_EN 120MHz High Frequency Internal Reference Clock Enable. 19 1 HIRC8_EN 7.3728MHz High Frequency Internal Reference Clock Enable. 20 1 HIRC8_VS 7.3728MHz Internal Oscillator Voltage Source Select 21 1 X32K_RDY 32KHz External Oscillator Ready. 25 1 CRYPTO_RDY 50MHz Internal Oscillator Ready. 26 1 HIRC96_RDY 120MHz Internal Oscillator Ready. 27 1 HIRC8_RDY 7.3728MHz Internal Oscillator Ready. 28 1 NANORING_RDY Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. 29 1 PMR Power Management. 0x0C MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 3 active Active Mode. 0 shutdown Shutdown Mode. 3 backup Backup Mode. 4 GPIOWKEN GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. 4 1 RTCWKEN RTC Wake Up Enable. This bit enables an RTC alarm to wake the device from any low-power mode to ACTIVE mode. 5 1 USBWKEN USB Wake Up Enable. This enables a USB wakeup event to cause the device to exit from all low power modes into ACTIVE mode. 6 1 CRYPTOPD Crypto Oscilator Power Down. This bit selects whether the oscillator is automatically powered down when the device transitions to DEEPSLEEP mode. 15 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 HIRC96PD 120MHz Internal Oscillator power down. This bit selects whether the oscillator is automatically powered down when the device transitions to DEEPSLEEP mode. 16 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 HIRC8PD 7.3728MHz Internal Oscillator power down. This bit selects whether the oscillator is automatically powered down when the device transitions to DEEPSLEEP mode. 17 1 active Mode is Active. 0 deepsleep Powered down in DEEPSLEEP. 1 PCLK_DIV Peripheral Clock Divider. 0x18 0x00000001 SDHCFRQ This bit selects the frequency of the SDHC clock. If set, the clock oscillates at 50Mhz, otherwise it will oscillate at 60MHz. 7 1 60M SDHC Freq = 120MHz/2. 0 50M SDHC Freq = 50Mhz. 1 ADCFRQ ADC Clock divider. ADC Clock Frequency = Periph_Clock/adcfrq. Values 0 and 1 invalid. 10 4 div2 ADC Freq = Periph_Clock/2. 2 div3 ADC Freq = Periph_Clock/3. 3 div4 ADC Freq = Periph_Clock/4. 4 div5 ADC Freq = Periph_Clock/5. 5 div6 ADC Freq = Periph_Clock/6. 6 div7 ADC Freq = Periph_Clock/7. 7 div8 ADC Freq = Periph_Clock/8. 8 div9 ADC Freq = Periph_Clock/9. 9 div10 ADC Freq = Periph_Clock/10. 10 div11 ADC Freq = Periph_Clock/11. 11 div12 ADC Freq = Periph_Clock/12. 12 div13 ADC Freq = Periph_Clock/13. 13 div14 ADC Freq = Periph_Clock/14. 14 div15 ADC Freq = Periph_Clock/15. 15 AONDIV Always-ON (AON) domain CLock Divider. These bits define the AON domain clock divider. 14 2 div4 PCLK divide by 4. 0 div8 PCLK divide by 8. 1 div16 PCLK divide by 16. 2 div32 PCLK divide by 32. 3 PCLK_DIS0 Peripheral Clock Disable. 0x24 GPIO0 GPIO0 Clock Disable. 0 1 en enable it. 0 dis disable it. 1 GPIO1 GPIO1 Disable. 1 1 en enable it. 0 dis disable it. 1 GPIO2 GPIO2 Disable. 2 1 en enable it. 0 dis disable it. 1 USB USB Disable. 3 1 en enable it. 0 dis disable it. 1 TFT TFT Disable. 4 1 en enable it. 0 dis disable it. 1 DMA DMA Disable. 5 1 en enable it. 0 dis disable it. 1 SPI0 SPI 0 Disable. 6 1 en enable it. 0 dis disable it. 1 SPI1 SPI 1 Disable. 7 1 en enable it. 0 dis disable it. 1 SPI2 SPI 2 Disable. 8 1 en enable it. 0 dis disable it. 1 UART0 UART 0 Disable. 9 1 en enable it. 0 dis disable it. 1 UART1 UART 1 Disable. 10 1 en enable it. 0 dis disable it. 1 I2C0 I2C 0 Disable. 13 1 en enable it. 0 dis disable it. 1 TPU Trust Protection Unit Disable. 14 1 en enable it. 0 dis disable it. 1 TIMER0 Timer 0 Disable. 15 1 en enable it. 0 dis disable it. 1 TIMER1 Timer 1 Disable. 16 1 en enable it. 0 dis disable it. 1 TIMER2 Timer 2 Disable. 17 1 en enable it. 0 dis disable it. 1 TIMER3 Timer 3 Disable. 18 1 en enable it. 0 dis disable it. 1 TIMER4 Timer 4 Disable. 19 1 en enable it. 0 dis disable it. 1 TIMER5 Timer 5 Disable. 20 1 en enable it. 0 dis disable it. 1 ADC ADC Disable. 23 1 en enable it. 0 dis disable it. 1 I2C1 I2C 1 Disable. 28 1 en enable it. 0 dis disable it. 1 PT Pulse Train Engine Disable. 29 1 en enable it. 0 dis disable it. 1 SPIXIPF SPI-XIPF Disable. 30 1 en enable it. 0 dis disable it. 1 SPIXIPM XSPI Master Clock Disable. 31 1 en enable it. 0 dis disable it. 1 MEM_CLK Memory Clock Control Register. 0x28 FWS Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 1. 0 3 SYSRAM0LS System RAM 0 Light Sleep Mode. Write 1 to put RAM0 in light sleep power mode. 16 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM1LS System RAM 1 Light Sleep Mode. Write 1 to put RAM1 in light sleep power mode. 17 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM2LS System RAM 2 Light Sleep Mode. Write 1 to put RAM2 in light sleep power mode. 18 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM3LS System RAM 3 Light Sleep Mode. Write 1 to put RAM3 in light sleep power mode. 19 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM4LS System RAM 4 Light Sleep Mode. Write 1 to put RAM4 in light sleep power mode. 20 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM5LS System RAM 4 Light Sleep Mode. Write 1 to put RAM5 in light sleep power mode. 21 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SYSRAM6LS System RAM 4 Light Sleep Mode. Write 1 to put RAM6 in light sleep power mode. 22 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 ICACHELS ICache RAM Light Sleep Mode. 24 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 ICACHEXIPLS SPI-XIPF Instruction Cache RAM Light Sleep Mode. 25 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 SCACHELS Internal RAM Cache Light Sleep Mode. 26 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 CRYPTOLS Crypto RAM Light Sleep Mode. 27 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 USBLS USB FIFO Light Sleep Mode. 28 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 ROMLS ROM Light Sleep Mode. 29 1 active RAM is active. 0 light_sleep RAM is in Light Sleep mode. 1 MEM_ZERO Memory Zeroize Control. 0x2C SRAM0Z System RAM Block 0. 0 1 nop No operation/complete. 0 start Start operation. 1 SRAM1Z System RAM Block 1. 1 1 nop No operation/complete. 0 start Start operation. 1 SRAM2Z System RAM Block 2. 2 1 nop No operation/complete. 0 start Start operation. 1 SRAM3Z System RAM Block 3. 3 1 nop No operation/complete. 0 start Start operation. 1 SRAM4Z System RAM Block 4. 4 1 nop No operation/complete. 0 start Start operation. 1 SRAM5Z System RAM Block 5. 5 1 nop No operation/complete. 0 start Start operation. 1 SRAM6Z System RAM Block 6. 6 1 nop No operation/complete. 0 start Start operation. 1 ICACHEZ Instruction Cache (ICC0) zeroization. 8 1 nop No operation/complete. 0 start Start operation. 1 ICACHEXIPZ SPI-XIPF Instruction Cache (ICC1) zeroization. 9 1 nop No operation/complete. 0 start Start operation. 1 SCACHEDATAZ EMCC data zeroization. 10 1 nop No operation/complete. 0 start Start operation. 1 SCACHETAGZ EMCC tag zeroization. 11 1 nop No operation/complete. 0 start Start operation. 1 CRYPTOZ Crypto MAA Memory zeroization. 12 1 nop No operation/complete. 0 start Start operation. 1 USBFIFOZ USB FIFO zeroization. 13 1 nop No operation/complete. 0 start Start operation. 1 SYS_STAT System Status Register. 0x40 ICELOCK ARM ICE Lock Status. 0 1 unlocked ICE is unlocked. 0 locked ICE is locked. 1 CODEINTERR Flash SPI-XIPF Code Integrity Error Status Flag. 1 1 noerr . 0 err SPI-XIPF code integrity error. 1 SCMEMF HyperBus/Xccela Cache Memory Error Status Flag. 5 1 noerr Normal operation. 0 memfault HyperBus/Xccela cahce memory fault. 1 RST1 Reset 1. 0x44 I2C1 I2C1 Reset. 0 1 PT Pulse Train Reset. 1 1 SPIXIP SPI-XIPF Reset. 3 1 XSPIM XSPI Master Reset. 4 1 GPIO3 GPIO3 Reset. 5 1 SDHC SDHC Reset. 6 1 OWIRE One-Wire Reset. 7 1 WDT1 WDT1 Reset. 8 1 SPI3 SPI3 Reset. 9 1 I2S I2S (SPIMSS) Reset. 10 1 XIPR SPIXR Reset. 15 1 SEMA Semaphore Block Reset. 16 1 PCLK_DIS1 Peripheral Clock Disable. 0x48 UART2 UART2 Disable. 1 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 TRNG TRNG Disable. 2 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SFLC Secore Flash Controller Clock Disable. 3 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 HBC HyperBus/Xccela Clock Disable. 4 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 GPIO3 GPIO3 Disable. 6 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SCACHE System Cache Clock Disable. 7 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SDMA Smart DMA Clock Disable. 8 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SEMA Semaphore Block Clock Disable. 9 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SDHC SDHC Controller Clock Disable. 10 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 ICACHE Flash Instruction Cache Clock Disable. 11 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 ICACHEXIPF SPI-XIPF Flash Clock Disable. 12 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 OW One-Wire Clock Disable. 13 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SPI3 SPI3 Clock Disable. 14 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 I2S I2S (SPIMSS) Clock Disable. 15 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 SPIXIPR SPIXR RAM Clock Disable. 20 1 en Clock enabled to the peripheral. 0 dis Clock disabled to the peripheral. 1 EVENT_EN Event Enable Register. 0x4C DMAEVENT Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 dis DMA CTZ Event will not wake up the device. 0 en DMA CTZ Event Wake-up Enabled. 1 RXEVENT Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 dis A receive event is not generated when an external input transitions from low to high. 0 en A receive event is generated when external event is triggered. 1 TXEVENT Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. 2 1 dis Transmit event disabled. 0 en A transmit event is enabled on Send Event instruction. 1 REV Revision Register. 0x50 read-only REVISION Manufacturer Chip Revision. 0 16 SYS_STAT_IE System Status Interrupt Enable Register. 0x54 ICEULIE ARM ICE Unlock Interrupt Enable. 0 1 dis disabled. 0 en enabled. 1 CIEIE SPI-XIPF Code Intergrity Error Interrupt Enable. 1 1 dis disabled. 0 en enabled. 1 SCMFIE HyperBus/Xccela Cache Memory Fault Interrupt Enable. 5 1 dis disabled. 0 en enabled. 1 SIR System Initialization Registers. 0x40000400 read-only 0x00 0x400 registers SISTAT System Initialization Status Register. 0x000 read-only MAGIC Magic Word Validation. This bit is set by the system initialization block following power-up. 0 1 read-only read magicNotSet Magic word was not set (OTP has not been initialized properly). 0 magicSet Magic word was set (OTP contains valid settings). 1 CRCERR CRC Error Status. This bit is set by the system initialization block following power-up. 1 1 read-only read noError No CRC errors occurred during the read of the OTP memory block. 0 error A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. 1 ERRADDR Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x004 read-only ERRADDR 0 32 FSTAT funcstat register. 0x100 read-only FPU FPU Function. 0 1 no 0 yes 1 USB USB Device. 1 1 no 0 yes 1 ADC 10-bit Sigma Delta ADC. 2 1 no 0 yes 1 XIP XiP function. 3 1 no 0 yes 1 PBM Pixel Bit Manipulator Function. 4 1 no 0 yes 1 HBC Hyperbus Control Function. 5 1 no 0 yes 1 SDHC SDHC function. 6 1 no 0 yes 1 SMPHR SMPHR function. 7 1 no 0 yes 1 SCACHE SRCC function. 8 1 no 0 yes 1 SFSTAT secfuncstat register. 0x104 read-only TRNG TRNG function. 2 1 no 0 yes 1 AES AES function. 3 1 no 0 yes 1 SHA SHA function. 4 1 no 0 yes 1 MAA MAA function. 5 1 no 0 yes 1 TRIMSIR Trim System Initilazation Registers 0x40054000 0x00 0x400 registers rsv0 RFU 0x00 BB_SIR2 System Init. Configuration Register 2. 0x08 read-only BB_SIR3 System Init. Configuration Register 3. 0x0C read-only TMR0 32-bit reloadable timer that can be used for timing and event counting. Timers 0x40010000 0x00 0x1000 registers TMR0 TMR0 IRQ 5 CNT Count. This register stores the current timer count. 0x00 0x00000001 COUNT Current count on the timer. 0 32 CMP Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. 0x04 0x0000FFFF COMPARE Timer compare value. 0 32 PWM PWM. This register stores the value that is compared to the current timer count. 0x08 PWM Timer PWM match value. 0 32 INTR Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. 0x0C oneToClear IRQ Clear Interrupt. 0 1 CN Timer Control Register. 0x10 TMODE Timer Mode. 0 3 oneshot One Shot Mode. 0 continuous Continuous Mode. 1 counter Counter Mode. 2 pwm PWM Mode. 3 capture Capture Mode. 4 compare Compare Mode. 5 gated Gated Mode. 6 capturecompare Capture/Compare Mode. 7 PRES Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. 3 3 div1 Divide by 1. 0 div2 Divide by 2. 1 div4 Divide by 4. 2 div8 Divide by 8. 3 div16 Divide by 16. 4 div32 Divide by 32. 5 div64 Divide by 64. 6 div128 Divide by 128. 7 div256 Divide by 256. Additionally, TMRn->cn.pres3 must be set. 0 div512 Divide by 512. Additionally, TMRn->cn.pres3 must be set. 2 div1024 Divide by 1024. Additionally, TMRn->cn.pres3 must be set. 3 div2048 Divide by 2048. Additionally, TMRn->cn.pres3 must be set. 4 div4096 Divide by 4096. Additionally, TMRn->cn.pres3 must be set. 5 TPOL Timer input/output polarity bit. 6 1 activeHi Active High. 0 activeLo Active Low. 1 TEN Timer Enable. 7 1 dis Disable. 0 en Enable. 1 PRES3 MSB of prescaler value. 8 1 div1 Divide by 1. 0 div2 Divide by 2. 0 div4 Divide by 4. 0 div8 Divide by 8. 0 div16 Divide by 16. 0 div32 Divide by 32. 0 div64 Divide by 64. 0 div128 Divide by 128. 0 div256 Divide by 256. Additionally, TMRn->cn.pres3 must be set. 1 div512 Divide by 512. Additionally, TMRn->cn.pres3 must be set. 1 div1024 Divide by 1024. Additionally, TMRn->cn.pres3 must be set. 1 div2048 Divide by 2048. Additionally, TMRn->cn.pres3 must be set. 1 div4096 Divide by 4096. Additionally, TMRn->cn.pres3 must be set. 1 PWMSYNC Timer PWM Synchronization Mode Enable. 9 1 dis Disable. 0 en Enable. 1 NOLHPOL Timer PWM output 0A polarity bit. 10 1 normal Normal output polarity. 0 invert Inverted output polarity. 1 NOLLPOL Timer PWM output 0A' polarity bit. 11 1 normal Normal output polarity. 0 invert Inverted output polarity. 1 PWMCKBD Timer PWM output 0A Mode Disable. 12 1 dis Disable. 1 en Enable. 0 NOLCMP Timer Non-Overlapping Compare Register. 0x14 NOLLCMP Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. 0 8 NOLHCMP Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. 8 8 TMR1 32-bit reloadable timer that can be used for timing and event counting. 1 0x40011000 TMR1 TMR1 IRQ 6 TMR2 32-bit reloadable timer that can be used for timing and event counting. 2 0x40012000 TMR2 TMR2 IRQ 7 TPU The Trust Protection Unit used to assist the computationally intensive operations of several common cryptographic algorithms. 0x40001000 0x00 0x1000 registers Crypto_Engine Crypto Engine interrupt. 27 CRYPTO_CTRL Crypto Control Register. 0x00 0xC0000000 RST Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle. 0 1 reset_write write reset Starts reset operation. 1 reset_read read reset_done Reset complete. 0 busy Reset in progress. 1 INT Interrupt Enable. Generates an interrupt when done or error set. 1 1 dis Disable 0 en Enable 1 SRC Source Select. This bit selects the hash function and CRC generator input source. 2 1 inputFIFO Input FIFO 0 outputFIFO Output FIFO 1 BSO Byte Swap Output. Note. No byte swap will occur if there is not a full word. 4 1 dis Disable 0 en Enable 1 BSI Byte Swap Input. Note. No byte swap will occur if there is not a full word. 5 1 dis Disable 0 en Enable 1 WAIT_EN Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready. 6 1 dis Disable 0 en Enable 1 WAIT_POL Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state. 7 1 activeLo Active Low. 0 activeHi Active High. 1 WRSRC Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled. 8 2 none None. 0 cipherOutput Cipher Output. 1 readFIFO Read FIFO. 2 RDSRC Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator. 10 2 dmaDisabled DMA Disable. 0 dmaOrApb DMA Or APB. 1 rng RNG. 2 FLAG_MODE Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs. 14 1 unres_wr Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags. 0 res_wr Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect. 1 DMADNEMSK DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA. 15 1 not_used DMA_DONE not used in setting CRYPTO_CTRL.DONE bit. 0 used DMA_DONE used in setting CRYPTO_CTRL.DONE bit. 1 DMA_DONE DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation. 24 1 notDone Not Done. 0 done Done. 1 GLS_DONE Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator. 25 1 notDone Not Done. 0 done Done. 1 HSH_DONE Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation. 26 1 notDone Not Done. 0 done Done. 1 CPH_DONE Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation. 27 1 notDone Not Done. 0 done Done. 1 MAA_DONE MAA Done. MAA operation is complete. This bit must be cleared before starting a new MAA operation. This bit is read only while the MAA is in progress. This bit is negate of MAA_CTRL.STC. 28 1 notDone Not Done. 0 done Done. 1 ERR AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block. 29 1 read-only noError No Error. 0 error Error. 1 RDY Ready. Crypto block ready for more data. 30 1 read-only busy Busy. 0 ready Ready. 1 DONE Done. One or more cryptographic calculations complete (logical OR of done flags). 31 1 read-only notDone Not Done. 0 done Done. 1 CIPHER_CTRL Cipher Control Register. 0x04 ENC Encrypt. Select encryption or decryption of input data. 0 1 encrypt Encrypt. 0 decrypt Decrypt. 1 KEY Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag. 1 1 complete No operation/complete. 0 start Start operation. 1 SRC Source of Random key. 2 2 cipherKey User cipher key (0x4000_1060). 0 regFile Key from battery-backed register file (0x4000_5000 to 0x4000_501F). 2 qspiKey_regFile Key from battery-backed register file (0x4000_5020 to 0x4000_502F). 3 CIPHER Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation. 4 3 dis Disabled. 0 aes128 AES 128. 1 aes192 AES 192. 2 aes256 AES 256. 3 des DES. 4 tdea Triple DES. 5 MODE Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes. 8 3 ECB ECB Mode. 0 CBC CBC Mode. 1 CFB CFB (AES only). 2 OFB OFB (AES only). 3 CTR CTR (AES only). 4 HASH_CTRL HASH Control Register. 0x08 INIT Initialize. Initializes hash registers with standard constants. 0 1 nop No operation/complete. 0 start Start operation. 1 XOR XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad. 1 1 dis Disable. 0 en Enable. 1 HASH Hash function selection. 2 3 dis Disabled. 0 sha1 SHA-1. 1 sha224 SHA 224. 2 sha256 SHA 256. 3 sha384 SHA 384. 4 sha512 SHA 512. 5 LAST Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash. 5 1 noEffect No Effect. 0 lastMsgData Last Message Data. 1 CRC_CTRL CRC Control Register. 0x0C CRC_EN Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled. 0 1 dis Disable. 0 en Enable. 1 MSB MSB select. This bit selects the order of calculating CRC on data. 1 1 lsbFirst LSB First. 0 msbFirst MSB First. 1 PRNG Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle. 2 1 dis Disable. 0 en Enable. 1 ENT Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source. 3 1 dis Disable. 0 en Enable. 1 HAM Hamming Code Enable. Enable hamming code calculation. 4 1 dis Disable. 0 en Enable. 1 HRST Hamming Reset. Reset Hamming code ECC generator for next block. 5 1 write-only write reset Starts reset operation. 1 DMA_SRC Crypto DMA Source Address. 0x10 ADDR DMA Source Address. 0 32 DMA_DEST Crypto DMA Destination Address. 0x14 ADDR DMA Destination Address. 0 32 DMA_CNT Crypto DMA Byte Count. 0x18 COUNT DMA Byte Address. 0 32 MAA_CTRL MAA Control Register. 0x1C STC Start Calculation. This bit functions as both the control and the status of the MAA. If the size value in the MAWS register is invalid, the STC bit will be cleared by hardware immediately. Otherwise, the STC bit is automatically cleared following the completion of each calculation or detecting an error. Clearing the STC bit resets the controller to its default state. 0 1 nop No operation/complete. 0 start Start operation. 1 CLC Calculation Configuration. These bits select desired calculation. 1 3 exp Exponentiation. 0 sq Square operation. 1 mult Multiplication. 2 sq_mult Square followed by a multiplication. 3 add Addition. 4 sub Subtraction. 5 OCALC Optimized Calculation Control. For optimized calculation, unnecessary multiply operations after normalizing the exponent are skipped. 4 1 none No optimization. 0 optimize Optimize calculation. 1 MAAER MAA Error. The MAAER bit defaults to 0 and can only be set by hardware. Once set, it must be cleared by software otherwise no new operation can be initiated. Software writes 1 to this bit has no effect and MAAER will maintain its original state. 7 1 noError No Error. 0 error Error. 1 AMS Multiplier A Memory Select. These bits select the starting position of the parameter 'a' within the logical segment specified by AMA. 8 2 BMS Multiplicand B Memory Select. These bits select the starting position of the parameter 'b' within the logical segment specified by BMA. 10 2 EMS Exponent Memory Select. These bits select the starting position of the parameter 'e' within the logical segment specified by EMA. 12 2 MMS Modulus Memory Select. These bits select the starting position of the parameter 'm' within the logical segment 5. 14 2 AMA Multiplier / Operand A Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'a'. 16 4 BMA Multiplicand / Operand B Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'b'. 20 4 RMA Result Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'r'. 24 4 TMA Temporary Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 't'. 28 4 4 4 CRYPTO_DIN[%s] Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register. 0x20 write-only DATA Crypto Data Input. Input can be written to this register instead of using DMA. 0 32 4 4 CRYPTO_DOUT[%s] Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits. 0x30 read-only DATA Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm. 0 32 CRC_POLY CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. 0x40 0xEDB88320 POLY CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit. 0 32 CRC_VAL CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit. 0x44 0xFFFFFFFF VAL CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit. 0 32 CRC_PRNG Pseudo Random Value. Output of the Galois Field shift register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled. 0x48 read-only PRNG Pseudo Random Value. Output of the Galois Field Shift Register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled. 0 32 HAM_ECC Hamming ECC Register. 0x4C ECC Hamming ECC Value. These bits are the even parity of their corresponding bit groups. 0 16 PAR Parity. This is the parity of the entire array. 16 1 even Even. 0 odd Odd. 1 4 4 CIPHER_INIT[%s] Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. 0x50 IVEC Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits. 0 32 8 4 CIPHER_KEY[%s] Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits. 0x60 write-only KEY Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits. 0 32 16 4 HASH_DIGEST[%s] This register holds the calculated hash value. This register is affected by the endian swap bits. 0x80 HASH This register holds the calculated hash value. This register is affected by the endian swap bits. 0 32 4 4 HASH_MSG_SZ[%s] Message Size. This register holds the lowest 32-bit of message size in bytes. 0xC0 MSGSZ Message Size. This register holds the lowest 32-bit of message size in bytes. 0 32 MAA_MAWS MAA Word Size. This register defines the number of bits for a modular operation. This register must be set to a valid value prior to the MAA operation start. Valid values are from 1 to 2048. Invalid values are ignored and will not initiate a MAA operation. 0xD0 MSGSZ MAA Word Size. 0 12 TRNG Random Number Generator. 0x400B5000 0x00 0x1000 registers TRNG TRNG interrupt. 4 CTRL TRNG Control Register. 0x00 0xFFFFFFC0 RNG_IE To enable IRQ generation when a new 32-bit Random number is ready. 2 1 dis Disable 0 en Enable 1 RNG_ISC Clears the RNG interrupt occuring after an 128-bit random number is ready. 3 1 clear Clear the RNG interrupt. 1 RNG_I4S This bit is set when a new 128 bit random number is ready to be read (using 4 consecutive reads of TRNG_DATA. When set, an interrupt will be generated if TRNG_CTRL.rng_ie = 1. This bit is cleared by setting TRNG_CTRL.rng_isc. 4 1 not_ready 128-bit random number not ready. 0 ready 128-bit random number ready. 1 RNG_IS This bit is set when a new 32 bit random number is available in TRNG_DATA. 5 1 not_ready 32-bit random number not ready. 0 ready 32-bit random number ready. 1 AESKG When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register. 6 1 DATA Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. 0x04 read-only DATA Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. 0 32 UART0 UART 0x40042000 0 0x1000 registers UART0 UART0 IRQ 14 CTRL0 Control Register. 0x00 32 ENABLE UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled. 0 1 dis UART disabled. FIFOs are flushed. Clock is gated off for power savings. 0 en UART enabled. 1 PARITY_EN Enable/disable Parity bit (9th character). 1 1 dis No Parity 0 en Parity enabled as 9th bit 1 PARITY_MODE When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1; Space parity = always 0. 2 2 even Even parity selected. 0 odd Odd parity selected. 1 mark Mark parity selected. 2 space Space parity selected. 3 PARITY_LVL Selects parity based on 1s or 0s count (when PARITY_EN=1). 4 1 ZERO Parity calculation is based on number of 0s in frame. 0 ONE Parity calculation is based on number of 1s in frame. 1 TXFLUSH Flushes the TX FIFO buffer. 5 1 nop No flush operation in progress/no effect. 0 flush TX FIFO flush initiation or flush operation currently in progress. 1 RXFLUSH Flushes the RX FIFO buffer. 6 1 nop No flush operation in progress/no effect. 0 flush RX FIFO flush initiation or flush operation currently in progress. 1 BITACC If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation. 7 1 frame Frame accuracy. 0 bit Bit accuracy. 1 SIZE Selects UART character size. 8 2 5bit_data 5 bits. 0 6bit_data 6 bits. 1 7bit_data 7 bits. 2 8bit_data 8 bits. 3 STOP Selects the number of stop bits that will be generated. 10 1 1_stopbits 1 stop bit. 0 2_stopbits 1.5 stop bits if the character size is 5, 2 stop bits for all other character sizes. 1 FLOW Enables/disables hardware flow control. 11 1 dis HW Flow Control disabled 0 en HW Flow Control with RTS/CTS enabled 1 FLOWPOL RTS/CTS polarity. 12 1 active_low RTS/CTS asserted is logic 0. 0 active_high RTS/CTS asserted is logic 1. 1 NULLMOD NULL Modem Support (RTS/CTS and TXD/RXD swap). 13 1 normal Direct convention. 0 swapped Null Modem Mode. RTS/CTS swapped and TX/RX swapped. 1 BREAK Break control bit. It causes a break condition to be transmitted to receiving UART. 14 1 normal Break characters are not generated. 0 break Break characters are sent (all the bits are at '0' including start/parity/stop). 1 CLK_SEL Baud Rate Clock Source Select. Selects the baud rate clock. 15 1 periph_clk System clock. 0 alt_clk Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. 1 TO_CNT RX Time Out. RX time out interrupt will occur after TO_CNT Uart characters if RX-FIFO is not empty and RX FIFO has not been read. 16 8 CTRL1 Threshold Control register. 0x04 32 RX_FIFO_LVL RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. 0 6 TX_FIFO_LVL TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. 8 6 RTS_FIFO_LVL RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. 16 6 STAT Status Register. 0x08 32 read-only TX_BUSY Read-only flag indicating the UART transmit status. 0 1 read-only idle The UART block is not currently transmitting chracters. 0 busy UART block currently transmitting chracters. 1 RX_BUSY Read-only flag indicating the UARTreceiver status. 1 1 read-only idle The UART block is not currently receiving chracters. 0 busy UART block currently receiving chracters. 1 PARITY 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. 2 1 read-only 0 Received a parity bit of 0. 0 1 Received a parity bit of 1. 1 BREAK Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). 3 1 read-only recv Break frame received. 1 RX_EMPTY Read-only flag indicating the RX FIFO state. 4 1 read-only empty RX FIFO empty. 1 RX_FULL Read-only flag indicating the RX FIFO state. 5 1 read-only full RX FIFO full. 1 TX_EMPTY Read-only flag indicating the TX FIFO state. 6 1 read-only empty TX FIFO empty. 1 TX_FULL Read-only flag indicating the TX FIFO state. 7 1 read-only full TX FIFO empty. 1 RX_NUM Indicates the number of bytes currently in the RX FIFO. 8 6 read-only TX_NUM Indicates the number of bytes currently in the TX FIFO. 16 6 read-only RX_TO Receiver Timeout Status. Indicates if timeout has occurred. 24 1 read-only expired RX timeout has occurred. 1 INT_EN Interrupt Enable Register. 0x0C 32 RX_FRAME_ERROR Enable for RX Frame Error Interrupt. 0 1 dis RX Frame error interrupt disabled. 0 en RX Frame error interrupt enabled. 1 RX_PARITY_ERROR Enable for RX Parity Error interrupt. 1 1 dis RX Parity error interrupt disabled. 0 en RX Parity error interrupt enabled. 1 CTS Enable for CTS signal change interrupt. 2 1 dis CTS State Change interrupt disabled. 0 en CTS State Change interrupt enabled. 1 RX_OVERRUN Enable for RX FIFO OVerrun interrupt. 3 1 dis RX Overrun interrupt disabled. 0 en RX Overrun interrupt enabled. 1 RX_FIFO_LVL Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. 4 1 dis RX FIFO Threshold Level interrupt disabled. 0 en RX FIFO Threshold Level interrupt enabled. 1 TX_FIFO_AE Enable for interrupt when TX FIFO has only one byte remaining. 5 1 dis TX FIFO One byte remaining (almost empty) interrupt disabled. 0 en TX FIFO one byte remaining (almost empty) interrupt enabled. 1 TX_FIFO_LVL Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. 6 1 dis TX FIFO Threshold Level interrupt disabled. 0 en TX FIFO Threshold Level interrupt enabled. 1 BREAK Enable for received BREAK character interrupt. 7 1 dis Break character received interrupt disabled. 0 en Break character recevied interrupt enabled. 1 RX_TO Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). 8 1 dis RX Timeout interrupt disabled. 0 en RX Timeout interrupt enabled. 1 LAST_BREAK Enable for Last break character interrupt. 9 1 dis Last break frame received interrupt disabled. 0 en Last break frame received interrupt enabled. 1 INT_FL Interrupt Status Flags. 0x10 32 oneToClear FRAME FLAG for RX Frame Error Interrupt. 0 1 active Frame Error interrupt active. 1 PARITY FLAG for RX Parity Error interrupt. 1 1 active Receive parity error interrupt active. 1 CTS_CHANGE FLAG for CTS signal change interrupt. 2 1 active CTS State change interrupt active. 1 RX_OVR FLAG for RX FIFO Overrun interrupt. 3 1 active RX Overrun interrupt active. 1 RX_FIFO_LVL FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. 4 1 active RX FIFO Threshold level interrupt active. 1 TX_FIFO_AE FLAG for interrupt when TX FIFO has only one byte remaining. 5 1 active TX FIFO one byte remaining interrupt active. 1 TX_FIFO_LVL FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. 6 1 active TX FIFO threshold level interrupt active. 1 BREAK FLAG for received BREAK character interrupt. 7 1 active Break character received interrupt active. 1 RX_TO FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). 8 1 active Receive timeout expired interrupt active. 1 LAST_BREAK FLAG for Last break character interrupt. 9 1 active Last break character received interrupt active. 1 BAUD0 Baud rate register. Integer portion. 0x14 32 IBAUD Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). 0 12 CLKDIV FACTOR must be chosen to have IDIV> 0. factor used in calculation = 128 > > FACTOR. 16 3 div128 Baud Factor 128 0 div64 Baud Factor 64 1 div32 Baud Factor 32 2 div16 Baud Factor 16 3 div8 Baud Factor 8 4 BAUD1 Baud rate register. Decimal Setting. 0x18 32 DBAUD Decimal portion of baud rate divisor value. DIV = InputClock/ (factor*Baud Rate Frequency). DDIV= (DIV-IDIV) *128. 0 7 FIFO FIFO Data buffer. 0x1C 32 FIFO Load/unload location for TX and RX FIFO buffers. 0 8 DMA DMA Configuration. 0x20 32 TXDMA_EN TX DMA channel enable. 0 1 dis DMA is disabled 0 en DMA is enabled 1 RXDMA_EN RX DMA channel enable. 1 1 dis DMA is disabled 0 en DMA is enabled 1 TXDMA_LVL TX threshold for DMA transmission. 8 6 RXDMA_LVL RX threshold for DMA transmission. 16 6 TXFIFO Transmit FIFO Status register. 0x24 32 DATA Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned). 0 7 UART1 UART 1 0x40043000 UART1 UART1 IRQ 15 UART2 UART 2 0x40044000 UART2 UART2 IRQ 34 USBHS USB 2.0 High-speed Controller. 0x400B1000 0 0x1000 registers USB 2 FADDR Function address register. 0x00 8 0x00 ADDR Function address for this controller. 0 7 read-write UPDATE Set when ADDR is written, cleared when new address takes effect. 7 1 read-only POWER Power management register. 0x01 8 EN_SUSPENDM Enable SUSPENDM signal. 0 1 read-write SUSPEND Suspend mode detected. 1 1 read-only RESUME Generate resume signaling. 2 1 read-write RESET Bus reset detected. 3 1 read-only HS_MODE High-speed mode detected. 4 1 read-only HS_ENABLE High-speed mode enable. 5 1 read-write SOFTCONN Softconn. 6 1 read-write ISO_UPDATE Wait for SOF during Isochronous xfers. 7 1 read-write INTRIN Interrupt register for EP0 and IN EP1-15. 0x02 16 EP15_IN_INT Endpoint 15 interrupt. 15 1 read-only EP14_IN_INT Endpoint 14 interrupt. 14 1 read-only EP13_IN_INT Endpoint 13 interrupt. 13 1 read-only EP12_IN_INT Endpoint 12 interrupt. 12 1 read-only EP11_IN_INT Endpoint 11 interrupt. 11 1 read-only EP10_IN_INT Endpoint 10 interrupt. 10 1 read-only EP9_IN_INT Endpoint 9 interrupt. 9 1 read-only EP8_IN_INT Endpoint 8 interrupt. 8 1 read-only EP7_IN_INT Endpoint 7 interrupt. 7 1 read-only EP6_IN_INT Endpoint 6 interrupt. 6 1 read-only EP5_IN_INT Endpoint 5 interrupt. 5 1 read-only EP4_IN_INT Endpoint 4 interrupt. 4 1 read-only EP3_IN_INT Endpoint 3 interrupt. 3 1 read-only EP2_IN_INT Endpoint 2 interrupt. 2 1 read-only EP1_IN_INT Endpoint 1 interrupt. 1 1 read-only EP0_IN_INT Endpoint 0 interrupt. 0 1 read-only INTROUT Interrupt register for OUT EP 1-15. 0x04 16 EP15_OUT_INT Endpoint 15 interrupt. 15 1 read-only EP14_OUT_INT Endpoint 14 interrupt. 14 1 read-only EP13_OUT_INT Endpoint 13 interrupt. 13 1 read-only EP12_OUT_INT Endpoint 12 interrupt. 12 1 read-only EP11_OUT_INT Endpoint 11 interrupt. 11 1 read-only EP10_OUT_INT Endpoint 10 interrupt. 10 1 read-only EP9_OUT_INT Endpoint 9 interrupt. 9 1 read-only EP8_OUT_INT Endpoint 8 interrupt. 8 1 read-only EP7_OUT_INT Endpoint 7 interrupt. 7 1 read-only EP6_OUT_INT Endpoint 6 interrupt. 6 1 read-only EP5_OUT_INT Endpoint 5 interrupt. 5 1 read-only EP4_OUT_INT Endpoint 4 interrupt. 4 1 read-only EP3_OUT_INT Endpoint 3 interrupt. 3 1 read-only EP2_OUT_INT Endpoint 2 interrupt. 2 1 read-only EP1_OUT_INT Endpoint 1 interrupt. 1 1 read-only INTRINEN Interrupt enable for EP 0 and IN EP 1-15. 0x06 16 EP15_IN_INT_EN Endpoint 15 interrupt enable. 15 1 read-write EP14_IN_INT_EN Endpoint 14 interrupt enable. 14 1 read-write EP13_IN_INT_EN Endpoint 13 interrupt enable. 13 1 read-write EP12_IN_INT_EN Endpoint 12 interrupt enable. 12 1 read-write EP11_IN_INT_EN Endpoint 11 interrupt enable. 11 1 read-write EP10_IN_INT_EN Endpoint 10 interrupt enable. 10 1 read-write EP9_IN_INT_EN Endpoint 9 interrupt enable. 9 1 read-write EP8_IN_INT_EN Endpoint 8 interrupt enable. 8 1 read-write EP7_IN_INT_EN Endpoint 7 interrupt enable. 7 1 read-write EP6_IN_INT_EN Endpoint 6 interrupt enable. 6 1 read-write EP5_IN_INT_EN Endpoint 5 interrupt enable. 5 1 read-write EP4_IN_INT_EN Endpoint 4 interrupt enable. 4 1 read-write EP3_IN_INT_EN Endpoint 3 interrupt enable. 3 1 read-write EP2_IN_INT_EN Endpoint 2 interrupt enable. 2 1 read-write EP1_IN_INT_EN Endpoint 1 interrupt enable. 1 1 read-write EP0_INT_EN Endpoint 0 interrupt enable. 0 1 read-write INTROUTEN Interrupt enable for OUT EP 1-15. 0x08 16 EP15_OUT_INT_EN Endpoint 15 interrupt. 15 1 read-write EP14_OUT_INT_EN Endpoint 14 interrupt. 14 1 read-write EP13_OUT_INT_EN Endpoint 13 interrupt. 13 1 read-write EP12_OUT_INT_EN Endpoint 12 interrupt. 12 1 read-write EP11_OUT_INT_EN Endpoint 11 interrupt. 11 1 read-write EP10_OUT_INT_EN Endpoint 10 interrupt. 10 1 read-write EP9_OUT_INT_EN Endpoint 9 interrupt. 9 1 read-write EP8_OUT_INT_EN Endpoint 8 interrupt. 8 1 read-write EP7_OUT_INT_EN Endpoint 7 interrupt. 7 1 read-write EP6_OUT_INT_EN Endpoint 6 interrupt. 6 1 read-write EP5_OUT_INT_EN Endpoint 5 interrupt. 5 1 read-write EP4_OUT_INT_EN Endpoint 4 interrupt. 4 1 read-write EP3_OUT_INT_EN Endpoint 3 interrupt. 3 1 read-write EP2_OUT_INT_EN Endpoint 2 interrupt. 2 1 read-write EP1_OUT_INT_EN Endpoint 1 interrupt. 1 1 read-write INTRUSB Interrupt register for common USB interrupts. 0x0A 8 SOF_INT Start of Frame. 3 1 read-only RESET_INT Bus reset detected. 2 1 read-only RESUME_INT Resume detected. 1 1 read-only SUSPEND_INT Suspend detected. 0 1 read-only INTRUSBEN Interrupt enable for common USB interrupts. 0x0B 8 SOF_INT_EN Start of Frame. 3 1 read-write RESET_INT_EN Bus reset detected. 2 1 read-write RESUME_INT_EN Resume detected. 1 1 read-write SUSPEND_INT_EN Suspend detected. 0 1 read-write FRAME Frame number. 0x0C 16 FRAMENUM Read the last received frame number, that is the 11-bit frame number received in the SOF packet. 0 11 read-only INDEX Index for banked registers. 0x0E 8 INDEX Index Register Access Selector. 0 4 read-write TESTMODE USB 2.0 test mode enable register. 0x0F 8 FORCE_FS Force USB to Full-speed after reset. 5 1 read-write FORCE_HS Force USB to High-speed after reset. 4 1 read-write TEST_PKT Transmit fixed test packet. 3 1 read-write TEST_K Force USB to continuous K state. 2 1 read-write TEST_J Force USB to continuous J state. 1 1 read-write TEST_SE0_NAK Respond to any valid IN token with NAK. 0 1 read-write INMAXP Maximum packet size for INx endpoint (x == INDEX). 0x10 16 MAXPACKETSIZE Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9 0 11 NUMPACKMINUS1 Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases. 11 5 CSR0 Control status register for EP 0 (when INDEX == 0). 0x12 8 SERV_SETUP_END Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set 7 1 read-write SERV_OUTPKTRDY Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set. 6 1 read-write SEND_STALL Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set. 5 1 read-write SETUP_END Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear. 4 1 read-only DATA_END Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet. 3 1 read-write SENT_STALL Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear. 2 1 read-write INPKTRDY EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared. 1 1 read-write OUTPKTRDY EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO. 0 1 read-only INCSRL Control status lower register for INx endpoint (x == INDEX). CSR0 0x12 8 INCOMPTX Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear. 7 1 read-write CLRDATATOG Write 1 to clear IN endpoint data-toggle to 0. 6 1 read-write SENTSTALL Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear. 5 1 read-write SENDSTALL Send STALL Handshake. 4 1 read-only terminate Terminate STALL handhsake 0 respond Respond to an IN token with a STALL handshake 1 FLUSHFIFO Flush Next Packet from IN FIFO. Write 1 to clear 3 1 read-write UNDERRUN Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear 2 1 read-write FIFONOTEMPTY Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear. 1 1 read-write INPKTRDY IN Packet Ready. Write a 1 to clear 0 1 read-only INCSRU Control status upper register for INx endpoint (x == INDEX). 0x13 8 AUTOSET Auto Set inpktrdy. 7 1 read-write set USBHS_INCSRL_inpktrdy must be set by firmware. 0 auto USBHS_INCSRL_inpktrdy is automatically set. 1 ISO Isochronous Transfer Enable 6 1 read-write interrupt Enable IN Bulk and IN interrupt transfers. 0 isochronous Enable IN Isochronous transfers. 1 MODE Endpoint Direction Mode. 5 1 read-write out Endpoint direction is OUT. 0 in Endpoint direction is IN. 1 FRCDATATOG Force In Data - Toggle 3 1 read-write received Toggle data-toglge only when an ACK is received. 0 dontcare Toggle data-toggle regardless of ACK. 1 DPKTBUFDIS Double Packet Buffering Disable 1 1 read-write en Enable Double packet buffering. 0 dis Disable Double Packet Buffering. 1 OUTMAXP Maximum packet size for OUTx endpoint (x == INDEX). 0x14 16 NUMPACKMINUS1 Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize. 11 5 MAXPACKETSIZE Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9. 0 11 OUTCSRL Control status lower register for OUTx endpoint (x == INDEX). 0x16 8 CLRDATATOG 7 1 read-write SENTSTALL 6 1 read-write SENDSTALL 5 1 read-write FLUSHFIFO 4 1 read-write DATAERROR 3 1 read-only OVERRUN 2 1 read-write FIFOFULL 1 1 read-only OUTPKTRDY 0 1 read-write OUTCSRU Control status upper register for OUTx endpoint (x == INDEX). 0x17 8 AUTOCLEAR 7 1 read-write ISO 6 1 read-write DISNYET 4 1 read-write DPKTBUFDIS 1 1 read-write INCOMPRX 0 1 read-only COUNT0 Number of received bytes in EP 0 FIFO (INDEX == 0). 0x18 16 COUNT0 Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1 0 7 read-only OUTCOUNT Number of received bytes in OUT EPx FIFO (x == INDEX). COUNT0 0x18 16 OUTCOUNT Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO. 0 13 read-only FIFO0 Read for OUT data FIFO, write for IN data FIFO. 0x20 USBHS_FIFO0 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO1 Read for OUT data FIFO, write for IN data FIFO. 0x24 USBHS_FIFO1 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO2 Read for OUT data FIFO, write for IN data FIFO. 0x28 USBHS_FIFO2 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO3 Read for OUT data FIFO, write for IN data FIFO. 0x2c USBHS_FIFO3 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO4 Read for OUT data FIFO, write for IN data FIFO. 0x30 USBHS_FIFO4 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO5 Read for OUT data FIFO, write for IN data FIFO. 0x34 USBHS_FIFO5 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO6 Read for OUT data FIFO, write for IN data FIFO. 0x38 USBHS_FIFO6 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO7 Read for OUT data FIFO, write for IN data FIFO. 0x3c USBHS_FIFO7 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO8 Read for OUT data FIFO, write for IN data FIFO. 0x40 USBHS_FIFO8 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO9 Read for OUT data FIFO, write for IN data FIFO. 0x44 USBHS_FIFO9 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO10 Read for OUT data FIFO, write for IN data FIFO. 0x48 USBHS_FIFO10 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO11 Read for OUT data FIFO, write for IN data FIFO. 0x4c USBHS_FIFO11 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO12 Read for OUT data FIFO, write for IN data FIFO. 0x50 USBHS_FIFO12 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO13 Read for OUT data FIFO, write for IN data FIFO. 0x54 USBHS_FIFO13 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO14 Read for OUT data FIFO, write for IN data FIFO. 0x58 USBHS_FIFO14 USBHS Endpoint FIFO Read/Write Register. 0 32 FIFO15 Read for OUT data FIFO, write for IN data FIFO. 0x5c USBHS_FIFO15 USBHS Endpoint FIFO Read/Write Register. 0 32 HWVERS HWVERS 0x6c 16 USBHS_HWVERS USBHS Register. 0 16 EPINFO Endpoint hardware information. 0x78 8 OUTENDPOINTS 4 4 read-only INTENDPOINTS 0 4 read-only RAMINFO RAM width information. 0x79 8 RAMBITS 0 4 read-only SOFTRESET Software reset register. 0x7A 8 RSTXS 1 1 read-write RSTS 0 1 read-write CTUCH Chirp timeout timer setting. 0x80 16 C_T_UCH HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host. 0 16 CTHSRTN Sets delay between HS resume to UTM normal operating mode. 0x82 16 C_T_HSTRN High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation. 0 16 MXM_USB_REG_00 MXM_USB_REG_00 0x400 M31_PHY_UTMI_RESET M31_PHY_UTMI_RESET 0x404 M31_PHY_UTMI_VCONTROL M31_PHY_UTMI_VCONTROL 0x408 M31_PHY_CLK_EN M31_PHY_CLK_EN 0x40C M31_PHY_PONRST M31_PHY_PONRST 0x410 M31_PHY_NONCRY_RSTB M31_PHY_NONCRY_RSTB 0x414 M31_PHY_NONCRY_EN M31_PHY_NONCRY_EN 0x418 M31_PHY_U2_COMPLIANCE_EN M31_PHY_U2_COMPLIANCE_EN 0x420 M31_PHY_U2_COMPLIANCE_DAC_ADJ M31_PHY_U2_COMPLIANCE_DAC_ADJ 0x424 M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN 0x428 M31_PHY_CLK_RDY M31_PHY_CLK_RDY 0x42C M31_PHY_PLL_EN M31_PHY_PLL_EN 0x430 M31_PHY_BIST_OK M31_PHY_BIST_OK 0x434 M31_PHY_DATA_OE M31_PHY_DATA_OE 0x438 M31_PHY_OSCOUTEN M31_PHY_OSCOUTEN 0x43C M31_PHY_LPM_ALIVE M31_PHY_LPM_ALIVE 0x440 M31_PHY_HS_BIST_MODE M31_PHY_HS_BIST_MODE 0x444 M31_PHY_CORECLKIN M31_PHY_CORECLKIN 0x448 M31_PHY_XTLSEL M31_PHY_XTLSEL 0x44C M31_PHY_LS_EN M31_PHY_LS_EN 0x450 M31_PHY_DEBUG_SEL M31_PHY_DEBUG_SEL 0x454 M31_PHY_DEBUG_OUT M31_PHY_DEBUG_OUT 0x458 M31_PHY_OUTCLKSEL M31_PHY_OUTCLKSEL 0x45C M31_PHY_XCFGI_31_0 M31_PHY_XCFGI_31_0 0x460 M31_PHY_XCFGI_63_32 M31_PHY_XCFGI_63_32 0x464 M31_PHY_XCFGI_95_64 M31_PHY_XCFGI_95_64 0x468 M31_PHY_XCFGI_127_96 M31_PHY_XCFGI_127_96 0x46C M31_PHY_XCFGI_137_128 M31_PHY_XCFGI_137_128 0x470 M31_PHY_XCFG_HS_COARSE_TUNE_NUM M31_PHY_XCFG_HS_COARSE_TUNE_NUM 0x474 M31_PHY_XCFG_HS_FINE_TUNE_NUM M31_PHY_XCFG_HS_FINE_TUNE_NUM 0x478 M31_PHY_XCFG_FS_COARSE_TUNE_NUM M31_PHY_XCFG_FS_COARSE_TUNE_NUM 0x47C M31_PHY_XCFG_FS_FINE_TUNE_NUM M31_PHY_XCFG_FS_FINE_TUNE_NUM 0x480 M31_PHY_XCFG_LOCK_RANGE_MAX M31_PHY_XCFG_LOCK_RANGE_MAX 0x484 M31_PHY_XCFGI_LOCK_RANGE_MIN M31_PHY_XCFGI_LOCK_RANGE_MIN 0x488 M31_PHY_XCFG_OB_RSEL M31_PHY_XCFG_OB_RSEL 0x48C M31_PHY_XCFG_OC_RSEL M31_PHY_XCFG_OC_RSEL 0x490 M31_PHY_XCFGO M31_PHY_XCFGO 0x494 MXM_INT USB Added Maxim Interrupt Flag Register. 0x498 VBUS VBUS 0 1 NOVBUS NOVBUS 1 1 MXM_INT_EN USB Added Maxim Interrupt Enable Register. 0x49C VBUS VBUS 0 1 NOVBUS NOVBUS 1 1 MXM_SUSPEND USB Added Maxim Suspend Register. 0x4A0 SEL Suspend register 0 1 MXM_REG_A4 USB Added Maxim Power Status Register 0x4A4 VRST_VDDB_N_A VRST_VDDB_N_A 0 1 WDT0 Watchdog Timer 0 0x40003000 0x00 0x0400 registers WDT0 1 CTRL Watchdog Timer Control Register. 0x00 0x7FFFF000 INT_PERIOD Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 0 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 RST_PERIOD Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. 4 4 wdt2pow31 2**31 clock cycles. 0 wdt2pow30 2**30 clock cycles. 1 wdt2pow29 2**29 clock cycles. 2 wdt2pow28 2**28 clock cycles. 3 wdt2pow27 2^27 clock cycles. 4 wdt2pow26 2**26 clock cycles. 5 wdt2pow25 2**25 clock cycles. 6 wdt2pow24 2**24 clock cycles. 7 wdt2pow23 2**23 clock cycles. 8 wdt2pow22 2**22 clock cycles. 9 wdt2pow21 2**21 clock cycles. 10 wdt2pow20 2**20 clock cycles. 11 wdt2pow19 2**19 clock cycles. 12 wdt2pow18 2**18 clock cycles. 13 wdt2pow17 2**17 clock cycles. 14 wdt2pow16 2**16 clock cycles. 15 WDT_EN Watchdog Timer Enable. 8 1 dis Disable. 0 en Enable. 1 INT_FLAG Watchdog Timer Interrupt Flag. 9 1 oneToClear inactive No interrupt is pending. 0 pending An interrupt is pending. 1 INT_EN Watchdog Timer Interrupt Enable. 10 1 dis Disable. 0 en Enable. 1 RST_EN Watchdog Timer Reset Enable. 11 1 dis Disable. 0 en Enable. 1 RST_FLAG Watchdog Timer Reset Flag. 31 1 read-write noEvent The event has not occurred. 0 occurred The event has occurred. 1 RST Watchdog Timer Reset Register. 0x04 write-only WDT_RST Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled. 0 8 seq0 The first value to be written to reset the WDT. 0x000000A5 seq1 The second value to be written to reset the WDT. 0x0000005A WDT1 Watchdog Timer 0 1 0x40003400 WDT1 WDT1 IRQ 57