/** * @file gpio_regs.h * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. * @note This file is @generated. * @ingroup gpio_registers */ /****************************************************************************** * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), * Copyright (C) 2023-2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ******************************************************************************/ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_GPIO_REGS_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_GPIO_REGS_H_ /* **** Includes **** */ #include #ifdef __cplusplus extern "C" { #endif #if defined (__ICCARM__) #pragma system_include #endif #if defined (__CC_ARM) #pragma anon_unions #endif /// @cond /* If types are not defined elsewhere (CMSIS) define them here */ #ifndef __IO #define __IO volatile #endif #ifndef __I #define __I volatile const #endif #ifndef __O #define __O volatile #endif #ifndef __R #define __R volatile const #endif /// @endcond /* **** Definitions **** */ /** * @ingroup gpio * @defgroup gpio_registers GPIO_Registers * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. * @details Individual I/O for each GPIO */ /** * @ingroup gpio_registers * Structure type to access the GPIO Registers. */ typedef struct { __IO uint32_t en0; /**< \b 0x00: GPIO EN0 Register */ __IO uint32_t en0_set; /**< \b 0x04: GPIO EN0_SET Register */ __IO uint32_t en0_clr; /**< \b 0x08: GPIO EN0_CLR Register */ __IO uint32_t out_en; /**< \b 0x0C: GPIO OUT_EN Register */ __IO uint32_t out_en_set; /**< \b 0x10: GPIO OUT_EN_SET Register */ __IO uint32_t out_en_clr; /**< \b 0x14: GPIO OUT_EN_CLR Register */ __IO uint32_t out; /**< \b 0x18: GPIO OUT Register */ __O uint32_t out_set; /**< \b 0x1C: GPIO OUT_SET Register */ __O uint32_t out_clr; /**< \b 0x20: GPIO OUT_CLR Register */ __I uint32_t in; /**< \b 0x24: GPIO IN Register */ __IO uint32_t int_mod; /**< \b 0x28: GPIO INT_MOD Register */ __IO uint32_t int_pol; /**< \b 0x2C: GPIO INT_POL Register */ __IO uint32_t in_en; /**< \b 0x30: GPIO IN_EN Register */ __IO uint32_t int_en; /**< \b 0x34: GPIO INT_EN Register */ __IO uint32_t int_en_set; /**< \b 0x38: GPIO INT_EN_SET Register */ __IO uint32_t int_en_clr; /**< \b 0x3C: GPIO INT_EN_CLR Register */ __I uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ __R uint32_t rsv_0x44; __IO uint32_t int_clr; /**< \b 0x48: GPIO INT_CLR Register */ __IO uint32_t wake_en; /**< \b 0x4C: GPIO WAKE_EN Register */ __IO uint32_t wake_en_set; /**< \b 0x50: GPIO WAKE_EN_SET Register */ __IO uint32_t wake_en_clr; /**< \b 0x54: GPIO WAKE_EN_CLR Register */ __R uint32_t rsv_0x58; __IO uint32_t int_dual_edge; /**< \b 0x5C: GPIO INT_DUAL_EDGE Register */ __IO uint32_t pdpu_sel0; /**< \b 0x60: GPIO PDPU_SEL0 Register */ __IO uint32_t pdpu_sel1; /**< \b 0x64: GPIO PDPU_SEL1 Register */ __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ __R uint32_t rsv_0x74_0xaf[15]; __IO uint32_t ds_sel0; /**< \b 0xB0: GPIO DS_SEL0 Register */ __IO uint32_t ds_sel1; /**< \b 0xB4: GPIO DS_SEL1 Register */ __IO uint32_t pssel; /**< \b 0xB8: GPIO PSSEL Register */ } mxc_gpio_regs_t; /* Register offsets for module GPIO */ /** * @ingroup gpio_registers * @defgroup GPIO_Register_Offsets Register Offsets * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. * @{ */ #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ #define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ #define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ #define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ #define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ #define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ #define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ #define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ #define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ #define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ #define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ #define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ #define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ #define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ #define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ #define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ #define MXC_R_GPIO_PDPU_SEL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ #define MXC_R_GPIO_PDPU_SEL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ #define MXC_R_GPIO_DS_SEL0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ #define MXC_R_GPIO_DS_SEL1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ #define MXC_R_GPIO_PSSEL ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ /**@} end of group gpio_registers */ /** * @ingroup gpio_registers * @defgroup GPIO_EN0 GPIO_EN0 * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one * GPIO pin on the associated port. * @{ */ #define MXC_F_GPIO_EN0_GPIO_EN0_POS 0 /**< EN0_GPIO_EN0 Position */ #define MXC_F_GPIO_EN0_GPIO_EN0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN0_POS)) /**< EN0_GPIO_EN0 Mask */ #define MXC_V_GPIO_EN0_GPIO_EN0_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN0_ALTERNATE Value */ #define MXC_S_GPIO_EN0_GPIO_EN0_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN0_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN0_POS) /**< EN0_GPIO_EN0_ALTERNATE Setting */ #define MXC_V_GPIO_EN0_GPIO_EN0_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN0_GPIO Value */ #define MXC_S_GPIO_EN0_GPIO_EN0_GPIO (MXC_V_GPIO_EN0_GPIO_EN0_GPIO << MXC_F_GPIO_EN0_GPIO_EN0_POS) /**< EN0_GPIO_EN0_GPIO Setting */ /**@} end of group GPIO_EN0_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_EN0_SET GPIO_EN0_SET * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this * register sets the bits in the same positions in GPIO_EN to 1, without affecting * other bits in that register. * @{ */ #define MXC_F_GPIO_EN0_SET_GPIO_EN0_SET_POS 0 /**< EN0_SET_GPIO_EN0_SET Position */ #define MXC_F_GPIO_EN0_SET_GPIO_EN0_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_GPIO_EN0_SET_POS)) /**< EN0_SET_GPIO_EN0_SET Mask */ /**@} end of group GPIO_EN0_SET_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this * register clears the bits in the same positions in GPIO_EN to 0, without * affecting other bits in that register. * @{ */ #define MXC_F_GPIO_EN0_CLR_GPIO_EN0_CLR_POS 0 /**< EN0_CLR_GPIO_EN0_CLR Position */ #define MXC_F_GPIO_EN0_CLR_GPIO_EN0_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_GPIO_EN0_CLR_POS)) /**< EN0_CLR_GPIO_EN0_CLR Mask */ /**@} end of group GPIO_EN0_CLR_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_OUT_EN GPIO_OUT_EN * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one * GPIO pin in the associated port. * @{ */ #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */ #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */ #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */ #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */ /**@} end of group GPIO_OUT_EN_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, * without affecting other bits in that register. * @{ */ #define MXC_F_GPIO_OUT_EN_SET_GPIO_OUT_EN_SET_POS 0 /**< OUT_EN_SET_GPIO_OUT_EN_SET Position */ #define MXC_F_GPIO_OUT_EN_SET_GPIO_OUT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_GPIO_OUT_EN_SET_POS)) /**< OUT_EN_SET_GPIO_OUT_EN_SET Mask */ /**@} end of group GPIO_OUT_EN_SET_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, * without affecting other bits in that register. * @{ */ #define MXC_F_GPIO_OUT_EN_CLR_GPIO_OUT_EN_CLR_POS 0 /**< OUT_EN_CLR_GPIO_OUT_EN_CLR Position */ #define MXC_F_GPIO_OUT_EN_CLR_GPIO_OUT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_GPIO_OUT_EN_CLR_POS)) /**< OUT_EN_CLR_GPIO_OUT_EN_CLR Mask */ /**@} end of group GPIO_OUT_EN_CLR_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_OUT GPIO_OUT * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the * associated port. This register can be written either directly, or by using the * GPIO_OUT_SET and GPIO_OUT_CLR registers. * @{ */ #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ /**@} end of group GPIO_OUT_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_OUT_SET GPIO_OUT_SET * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits * in the same positions in GPIO_OUT to 1, without affecting other bits in that * register. * @{ */ #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ /**@} end of group GPIO_OUT_SET_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the * bits in the same positions in GPIO_OUT to 0, without affecting other bits in * that register. * @{ */ #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ /**@} end of group GPIO_OUT_CLR_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_IN GPIO_IN * @brief GPIO Input Register. Read-only register to read from the logic states of the * GPIO pins on this port. * @{ */ #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ /**@} end of group GPIO_IN_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_INT_MOD GPIO_INT_MOD * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt * mode setting for the associated GPIO pin on this port. * @{ */ #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */ #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */ #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */ #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */ /**@} end of group GPIO_INT_MOD_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_INT_POL GPIO_INT_POL * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the * interrupt polarity setting for one GPIO pin in the associated port. * @{ */ #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */ #define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */ #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */ #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */ /**@} end of group GPIO_INT_POL_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_IN_EN GPIO_IN_EN * @brief GPIO Input Enable * @{ */ #define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0 /**< IN_EN_GPIO_IN_EN Position */ #define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) /**< IN_EN_GPIO_IN_EN Mask */ #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_NOT_CONNECTED ((uint32_t)0x0UL) /**< IN_EN_GPIO_IN_EN_NOT_CONNECTED Value */ #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_NOT_CONNECTED (MXC_V_GPIO_IN_EN_GPIO_IN_EN_NOT_CONNECTED << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_NOT_CONNECTED Setting */ #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_CONNECTED ((uint32_t)0x1UL) /**< IN_EN_GPIO_IN_EN_CONNECTED Value */ #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_CONNECTED (MXC_V_GPIO_IN_EN_GPIO_IN_EN_CONNECTED << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_CONNECTED Setting */ /**@} end of group GPIO_IN_EN_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_INT_EN GPIO_INT_EN * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO * interrupt enable for the associated pin on the GPIO port. * @{ */ #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */ #define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */ #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */ #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */ /**@} end of group GPIO_INT_EN_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits * in that register. * @{ */ #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */ #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */ #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */ /**@} end of group GPIO_INT_EN_SET_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting * other bits in that register. * @{ */ #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */ #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */ #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */ /**@} end of group GPIO_INT_EN_CLR_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_INT_STAT GPIO_INT_STAT * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending * interrupt status for the associated GPIO pin in this port. * @{ */ #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */ #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */ #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */ #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */ /**@} end of group GPIO_INT_STAT_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_INT_CLR GPIO_INT_CLR * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits * in that register. * @{ */ #define MXC_F_GPIO_INT_CLR_GPIO_INT_CLR_POS 0 /**< INT_CLR_GPIO_INT_CLR Position */ #define MXC_F_GPIO_INT_CLR_GPIO_INT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_GPIO_INT_CLR_POS)) /**< INT_CLR_GPIO_INT_CLR Mask */ /**@} end of group GPIO_INT_CLR_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_WAKE_EN GPIO_WAKE_EN * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup * enable for the associated GPIO pin in this port. * @{ */ #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */ #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */ #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */ /**@} end of group GPIO_WAKE_EN_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in * that register. * @{ */ #define MXC_F_GPIO_WAKE_EN_SET_GPIO_WAKE_EN_SET_POS 0 /**< WAKE_EN_SET_GPIO_WAKE_EN_SET Position */ #define MXC_F_GPIO_WAKE_EN_SET_GPIO_WAKE_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_GPIO_WAKE_EN_SET_POS)) /**< WAKE_EN_SET_GPIO_WAKE_EN_SET Mask */ /**@} end of group GPIO_WAKE_EN_SET_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other * bits in that register. * @{ */ #define MXC_F_GPIO_WAKE_EN_CLR_GPIO_WAKE_EN_CLR_POS 0 /**< WAKE_EN_CLR_GPIO_WAKE_EN_CLR Position */ #define MXC_F_GPIO_WAKE_EN_CLR_GPIO_WAKE_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_GPIO_WAKE_EN_CLR_POS)) /**< WAKE_EN_CLR_GPIO_WAKE_EN_CLR Mask */ /**@} end of group GPIO_WAKE_EN_CLR_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual * edge mode for the associated GPIO pin in this port. * @{ */ #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */ #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */ #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */ /**@} end of group GPIO_INT_DUAL_EDGE_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_PDPU_SEL0 GPIO_PDPU_SEL0 * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for * the associated GPIO pin in this port. * @{ */ #define MXC_F_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_POS 0 /**< PDPU_SEL0_GPIO_PDPU_SEL0 Position */ #define MXC_F_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_POS)) /**< PDPU_SEL0_GPIO_PDPU_SEL0 Mask */ #define MXC_V_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_IMPEDANCE ((uint32_t)0x0UL) /**< PDPU_SEL0_GPIO_PDPU_SEL0_IMPEDANCE Value */ #define MXC_S_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_IMPEDANCE (MXC_V_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_IMPEDANCE << MXC_F_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_POS) /**< PDPU_SEL0_GPIO_PDPU_SEL0_IMPEDANCE Setting */ #define MXC_V_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_PU ((uint32_t)0x1UL) /**< PDPU_SEL0_GPIO_PDPU_SEL0_PU Value */ #define MXC_S_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_PU (MXC_V_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_PU << MXC_F_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_POS) /**< PDPU_SEL0_GPIO_PDPU_SEL0_PU Setting */ #define MXC_V_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_PD ((uint32_t)0x2UL) /**< PDPU_SEL0_GPIO_PDPU_SEL0_PD Value */ #define MXC_S_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_PD (MXC_V_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_PD << MXC_F_GPIO_PDPU_SEL0_GPIO_PDPU_SEL0_POS) /**< PDPU_SEL0_GPIO_PDPU_SEL0_PD Setting */ /**@} end of group GPIO_PDPU_SEL0_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_PDPU_SEL1 GPIO_PDPU_SEL1 * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for * the associated GPIO pin in this port. * @{ */ #define MXC_F_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_POS 0 /**< PDPU_SEL1_GPIO_PDPU_SEL1 Position */ #define MXC_F_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_POS)) /**< PDPU_SEL1_GPIO_PDPU_SEL1 Mask */ #define MXC_V_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_IMPEDANCE ((uint32_t)0x0UL) /**< PDPU_SEL1_GPIO_PDPU_SEL1_IMPEDANCE Value */ #define MXC_S_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_IMPEDANCE (MXC_V_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_IMPEDANCE << MXC_F_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_POS) /**< PDPU_SEL1_GPIO_PDPU_SEL1_IMPEDANCE Setting */ #define MXC_V_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_PU ((uint32_t)0x1UL) /**< PDPU_SEL1_GPIO_PDPU_SEL1_PU Value */ #define MXC_S_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_PU (MXC_V_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_PU << MXC_F_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_POS) /**< PDPU_SEL1_GPIO_PDPU_SEL1_PU Setting */ #define MXC_V_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_PD ((uint32_t)0x2UL) /**< PDPU_SEL1_GPIO_PDPU_SEL1_PD Value */ #define MXC_S_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_PD (MXC_V_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_PD << MXC_F_GPIO_PDPU_SEL1_GPIO_PDPU_SEL1_POS) /**< PDPU_SEL1_GPIO_PDPU_SEL1_PD Setting */ /**@} end of group GPIO_PDPU_SEL1_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_EN1 GPIO_EN1 * @brief GPIO Alternate Function Enable Register. Each bit in this register selects * between primary/secondary functions for the associated GPIO pin in this port. * @{ */ #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ /**@} end of group GPIO_EN1_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_EN1_SET GPIO_EN1_SET * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other * bits in that register. * @{ */ #define MXC_F_GPIO_EN1_SET_GPIO_EN1_SET_POS 0 /**< EN1_SET_GPIO_EN1_SET Position */ #define MXC_F_GPIO_EN1_SET_GPIO_EN1_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_GPIO_EN1_SET_POS)) /**< EN1_SET_GPIO_EN1_SET Mask */ /**@} end of group GPIO_EN1_SET_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other * bits in that register. * @{ */ #define MXC_F_GPIO_EN1_CLR_GPIO_EN1_CLR_POS 0 /**< EN1_CLR_GPIO_EN1_CLR Position */ #define MXC_F_GPIO_EN1_CLR_GPIO_EN1_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_GPIO_EN1_CLR_POS)) /**< EN1_CLR_GPIO_EN1_CLR Mask */ /**@} end of group GPIO_EN1_CLR_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_DS_SEL0 GPIO_DS_SEL0 * @brief GPIO Drive Strength Register. Each bit in this register selects the drive * strength for the associated GPIO pin in this port. Refer to the Datasheet for * sink/source current of GPIO pins in each mode. * @{ */ #define MXC_F_GPIO_DS_SEL0_DS_SEL0_POS 0 /**< DS_SEL0_DS_SEL0 Position */ #define MXC_F_GPIO_DS_SEL0_DS_SEL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_SEL0_DS_SEL0_POS)) /**< DS_SEL0_DS_SEL0 Mask */ #define MXC_V_GPIO_DS_SEL0_DS_SEL0_LD ((uint32_t)0x0UL) /**< DS_SEL0_DS_SEL0_LD Value */ #define MXC_S_GPIO_DS_SEL0_DS_SEL0_LD (MXC_V_GPIO_DS_SEL0_DS_SEL0_LD << MXC_F_GPIO_DS_SEL0_DS_SEL0_POS) /**< DS_SEL0_DS_SEL0_LD Setting */ #define MXC_V_GPIO_DS_SEL0_DS_SEL0_HD ((uint32_t)0x1UL) /**< DS_SEL0_DS_SEL0_HD Value */ #define MXC_S_GPIO_DS_SEL0_DS_SEL0_HD (MXC_V_GPIO_DS_SEL0_DS_SEL0_HD << MXC_F_GPIO_DS_SEL0_DS_SEL0_POS) /**< DS_SEL0_DS_SEL0_HD Setting */ /**@} end of group GPIO_DS_SEL0_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_DS_SEL1 GPIO_DS_SEL1 * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive * strength for the associated GPIO pin in this port. Refer to the Datasheet for * sink/source current of GPIO pins in each mode. * @{ */ #define MXC_F_GPIO_DS_SEL1_DS_SEL1_POS 0 /**< DS_SEL1_DS_SEL1 Position */ #define MXC_F_GPIO_DS_SEL1_DS_SEL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_SEL1_DS_SEL1_POS)) /**< DS_SEL1_DS_SEL1 Mask */ /**@} end of group GPIO_DS_SEL1_Register */ /** * @ingroup gpio_registers * @defgroup GPIO_PSSEL GPIO_PSSEL * @brief GPIO Pull Select Mode. * @{ */ #define MXC_F_GPIO_PSSEL_PSSEL_POS 0 /**< PSSEL_PSSEL Position */ #define MXC_F_GPIO_PSSEL_PSSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PSSEL_PSSEL_POS)) /**< PSSEL_PSSEL Mask */ /**@} end of group GPIO_PSSEL_Register */ #ifdef __cplusplus } #endif #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_GPIO_REGS_H_