/*
 * Copyright 2023 NXP
 * SPDX-License-Identifier: Apache-2.0
 */

#define SCG_K4_CORESYS_CLK 0U
#define SCG_K4_SLOW_CLK    1U
#define SCG_K4_PLAT_CLK    2U
#define SCG_K4_SYS_CLK     3U
#define SCG_K4_BUS_CLK     4U
#define SCG_K4_SYSOSC_CLK  5U
#define SCG_K4_SIRC_CLK    6U
#define SCG_K4_FIRC_CLK    7U
#define SCG_K4_RTCOSC_CLK  8U