/*
 * Copyright (c) 2024 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "nrf54l_05_10_15.dtsi"

&cpuapp_sram {
	reg = <0x20000000 DT_SIZE_K(144)>;
	ranges = <0x0 0x20000000 DT_SIZE_K(144)>;
};

/* 144 + 48 = 192KB */
/ {
	soc {
		cpuflpr_sram: memory@20024000 {
			compatible = "mmio-sram";
			reg = <0x20024000 DT_SIZE_K(48)>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x20024000 DT_SIZE_K(48)>;
		};
	};
};

&cpuapp_rram {
	reg = <0x0 DT_SIZE_K(960)>;
};

/* 960 + 62 = 1022KB */
&rram_controller {
	cpuflpr_rram: rram@f0000 {
		compatible = "soc-nv-flash";
		reg = <0xf0000 DT_SIZE_K(62)>;
		erase-block-size = <4096>;
		write-block-size = <16>;
	};
};