/* * Copyright (c) 2024 Nuvoton Technology Corporation. * * SPDX-License-Identifier: Apache-2.0 */ /* Device tree declarations of npcm soc family */ #include "npcm.dtsi" #include / { soc { mdc: mdc@4000c000 { compatible = "syscon"; reg = <0x4000c000 0xa>; reg-io-width = <1>; }; mdc_header: mdc@4000c00a { compatible = "syscon"; reg = <0x4000c00a 0x4>; reg-io-width = <2>; }; pcc: clock-controller@4000d000 { clock-frequency = ; /* OFMCLK runs at 96MHz */ core-prescaler = <1>; /* CORE_CLK runs at 96MHz */ apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */ apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */ apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */ ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */ fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */ i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */ }; }; soc-if { }; };