/* * Copyright 2022-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ #include &pinctrl { uart0_default: uart0_default { group1 { pinmux = ; output-enable; }; group2 { pinmux = ; input-enable; }; }; uart9_default: uart9_default { group1 { pinmux = ; output-enable; }; group2 { pinmux = ; input-enable; }; }; emdio_default: emdio_default { group1 { pinmux = <(PE10_ETH_MDC_I | PE10_ETH_MDC_O)>; input-enable; output-enable; }; group2 { pinmux = <(PE11_ETH_MDIO_I | PE11_ETH_MDIO_O)>; input-enable; output-enable; drive-open-drain; }; }; eth0_default: eth0_default { group1 { pinmux = , , , , , ; input-enable; }; group2 { pinmux = , , , , , ; output-enable; }; }; canxl0_default: canxl0_default { group1 { pinmux = ; input-enable; }; group2 { pinmux = ; output-enable; }; }; canxl1_default: canxl1_default { group1 { pinmux = ; input-enable; }; group2 { pinmux = ; output-enable; }; }; flexcan0_default: flexcan0_default { group1 { pinmux = ; input-enable; }; group2 { pinmux = ; output-enable; }; }; flexcan1_default: flexcan1_default { group1 { pinmux = ; input-enable; }; group2 { pinmux = ; output-enable; }; }; i2c1_default: i2c1_default { group1 { pinmux = <(PC15_I2C_1_SDA_I | PC15_I2C_1_SDA_O)>, <(PD0_I2C_1_SCL_I | PD0_I2C_1_SCL_O)>; input-enable; output-enable; drive-open-drain; }; }; i2c2_default: i2c2_default { group1 { pinmux = <(PJ11_I2C_2_SDA_I | PJ11_I2C_2_SDA_O)>, <(PJ10_I2C_2_SCL_I | PJ10_I2C_2_SCL_O)>; input-enable; output-enable; drive-open-drain; }; }; };