/*
 * Copyright 2021,2024 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include <nxp/nxp_rt11xx_cm7.dtsi>
#include "mimxrt1160_evk.dtsi"

/ {
	model = "NXP MIMXRT1160-EVK board";
	compatible = "nxp,mimxrt1166";

	chosen {
		zephyr,sram = &sdram0;
		zephyr,dtcm = &dtcm;
		zephyr,itcm = &itcm;
		zephyr,console = &lpuart1;
		zephyr,shell-uart = &lpuart1;
		zephyr,canbus = &flexcan3;
		zephyr,flash-controller = &is25wp128;
		zephyr,flash = &is25wp128;
		zephyr,code-partition = &slot0_partition;
		zephyr,cpu1-region = &ocram;
		zephyr,ipc = &mailbox_a;
	};

	sdram0: memory@80000000 {
		/* Winbond W9825G6KH-5I */
		device_type = "memory";
		reg = <0x80000000 DT_SIZE_M(64)>;
	};

	aliases {
		watchdog0 = &wdog1;
	};

	/*
	 * This node describes the GPIO pins mapping of the 44-pin camera
	 * connector, J2 on the EVK. This camera interface is supported
	 * on several NXP RT11xx EVKs, such as RT1170 and RT1160 EVK and
	 * is used with an ov5640 camera module available as a Zephyr shield
	 */
	nxp_cam_connector: cam-connector {
		compatible = "nxp,cam-44pins-connector";
		#gpio-cells = <2>;
		gpio-map-mask = <0xffffffff 0xffffffc0>;
		gpio-map-pass-thru = <0 0x3f>;
		gpio-map =	<9 0 &gpio11 15 0>,	/* Pin 9, RESETB */
				<17 0 &gpio9 25  0>;	/* Pin 17, PWDN */
	};

	/*
	 * This node describes the GPIO pins of the MIPI FPC interface,
	 * J48 on the EVK. This interface is standard to several
	 * NXP EVKs, and is used with several MIPI displays
	 * (available as zephyr shields)
	 */
	 nxp_mipi_connector: mipi-connector {
		compatible = "gpio-nexus";
		#gpio-cells = <2>;
		gpio-map-mask = <0xffffffff 0xffffffc0>;
		gpio-map-pass-thru = <0 0x3f>;
		gpio-map =	<0  0 &gpio9 29 0>,	/* Pin 1, LEDK */
				<21 0 &gpio9 1  0>,	/* Pin 21, RESET */
				<22 0 &gpio9 4  0>,	/* Pin 22, LPTE */
				<26 0 &gpio6 4  0>,	/* Pin 26, CTP_I2C SDA */
				<27 0 &gpio6 5  0>,	/* Pin 27, CTP_I2C SCL */
				<28 0 &gpio9 0  0>,	/* Pin 28, CTP_RST */
				<29 0 &gpio2 31 0>,	/* Pin 29, CTP_INT */
				<32 0 &gpio11 16 0>,	/* Pin 32, PWR_EN */
				<34 0 &gpio9 29 0>;	/* Pin 34, BL_PWM */
	};
};

&lpuart1 {
	status = "okay";
	current-speed = <115200>;
};

&flexcan3 {
	status = "okay";
	can-transceiver {
		max-bitrate = <5000000>;
	};
};

&lpi2c1 {
	status = "okay";
};

&lpspi1 {
	status = "okay";
};

/* GPT and Systick are enabled. If power management is enabled, the GPT
 * timer will be used instead of systick, as allows the core clock to
 * be gated.
 */
&gpt_hw_timer {
	status = "okay";
};

&systick {
	status = "okay";
};

&lpadc0 {
	status = "okay";
};

&wdog1 {
	status = "okay";
};

&edma0 {
	status = "okay";
};

zephyr_udc0: &usb1 {
	status = "okay";
};

&mailbox_a {
	status = "okay";
};

&pit1 {
	status = "okay";
};

&pit2 {
	status = "okay";
};

nxp_cam_i2c: &lpi2c6 {};

nxp_mipi_csi: &mipi_csi2rx {};

nxp_csi: &csi {};

zephyr_lcdif: &lcdif {};

zephyr_mipi_dsi: &mipi_dsi {
	dphy-ref-frequency = <24000000>;
};

nxp_mipi_i2c: &lpi2c5 {
	pinctrl-0 = <&pinmux_lpi2c5>;
	pinctrl-names = "default";
	#address-cells = <1>;
	#size-cells = <0>;
};