/* * Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or * an affiliate of Cypress Semiconductor Corporation * * SPDX-License-Identifier: Apache-2.0 */ /** * @brief Infineon PSoC 6 SOC. */ #include #include #include #include cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddress userIsr) { CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority)); cy_en_sysint_status_t status = CY_SYSINT_SUCCESS; /* The interrupt vector will be relocated only if the vector table was * moved to SRAM (CONFIG_DYNAMIC_INTERRUPTS and CONFIG_GEN_ISR_TABLES * must be enabled). Otherwise it is ignored. */ #if (CY_CPU_CORTEX_M0P) #error Cy_SysInt_Init does not support CM0p core. #endif /* (CY_CPU_CORTEX_M0P) */ #if defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES) if (config != NULL) { uint32_t priority; /* NOTE: * PendSV IRQ (which is used in Cortex-M variants to implement thread * context-switching) is assigned the lowest IRQ priority level. * If priority is same as PendSV, we will catch assertion in * z_arm_irq_priority_set function. To avoid this, change priority * to IRQ_PRIO_LOWEST, if it > IRQ_PRIO_LOWEST. Macro IRQ_PRIO_LOWEST * takes in to account PendSV specific. */ priority = (config->intrPriority > IRQ_PRIO_LOWEST) ? IRQ_PRIO_LOWEST : config->intrPriority; /* Configure a dynamic interrupt */ (void) irq_connect_dynamic(config->intrSrc, priority, (void *) userIsr, NULL, 0); } else { status = CY_SYSINT_BAD_PARAM; } #endif /* defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES) */ return status; } static int init_cycfg_platform_wraper(void) { /* Initializes the system */ SystemInit(); return 0; } SYS_INIT(init_cycfg_platform_wraper, PRE_KERNEL_1, 0);