/* * Copyright (c) 2020 TriaGnoSys GmbH * * SPDX-License-Identifier: Apache-2.0 */ #include #include #include #include #include #include / { chosen { zephyr,flash-controller = &msc; zephyr,entropy = &se; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m33"; reg = <0>; cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>; }; power-states { /* * EM1 is a basic "CPU WFI idle", all high-freq clocks remain * enabled. */ pstate_em1: em1 { compatible = "zephyr,power-state"; power-state-name = "runtime-idle"; min-residency-us = <4>; /* HFXO remains active */ exit-latency-us = <2>; }; /* * EM2 is a deepsleep with HF clocks disabled by HW, voltages * scaled down, etc. */ pstate_em2: em2 { compatible = "zephyr,power-state"; power-state-name = "suspend-to-idle"; min-residency-us = <260>; exit-latency-us = <250>; }; /* * EM3 seems to be exactly the same as EM2 except that * LFXO & LFRCO should be disabled, so you must use ULFRCO * as BURTC clock for the system to not lose track of time and * wake up. */ pstate_em3: em3 { compatible = "zephyr,power-state"; power-state-name = "standby"; min-residency-us = <20000>; exit-latency-us = <2000>; }; }; }; sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; }; soc { msc: flash-controller@50030000 { compatible = "silabs,gecko-flash-controller"; reg = <0x50030000 0x3148>; interrupts = <50 0>; #address-cells = <1>; #size-cells = <1>; flash0: flash@0 { compatible = "soc-nv-flash"; write-block-size = <4>; erase-block-size = <8192>; }; }; usart0: usart@5005c000 { compatible = "silabs,gecko-usart"; reg = <0x5005C000 0x306c>; interrupts = <9 0>, <10 0>; interrupt-names = "rx", "tx"; peripheral-id = <0>; status = "disabled"; }; burtc0: burtc@50064000 { compatible = "silabs,gecko-burtc"; reg = <0x50064000 0x3034>; interrupts = <17 0>; status = "disabled"; }; se: semailbox@5c021000 { compatible = "silabs,gecko-semailbox"; reg = <0x5c021000 0x1000>; status = "disabled"; interrupts = <64 3>, <65 3>, <66 3>; interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX"; }; i2c0: i2c@5b000000 { compatible = "silabs,gecko-i2c"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; reg = <0x5b000000 0x3044>; interrupts = <27 0>; status = "disabled"; }; stimer0: stimer@500a8000 { compatible = "silabs,gecko-stimer"; reg = <0x500a8000 0x3054>; interrupts = <67 0>; clock-frequency = <32768>; prescaler = <1>; status = "disabled"; }; gpio: gpio@5003c000 { compatible = "silabs,gecko-gpio"; reg = <0x5003c000 0x4000>; interrupts = <26 2>, <25 2>; interrupt-names = "GPIO_EVEN", "GPIO_ODD"; ranges; #address-cells = <1>; #size-cells = <1>; gpioa: gpio@5003c030 { compatible = "silabs,gecko-gpio-port"; reg = <0x5003c030 0x30>; peripheral-id = <0>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; gpiob: gpio@5003c060 { compatible = "silabs,gecko-gpio-port"; reg = <0x5003c060 0x30>; peripheral-id = <1>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; gpioc: gpio@5003c090 { compatible = "silabs,gecko-gpio-port"; reg = <0x5003c090 0x30>; peripheral-id = <2>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; gpiod: gpio@5003c0C0 { compatible = "silabs,gecko-gpio-port"; reg = <0x5003c0C0 0x30>; peripheral-id = <3>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; }; wdog0: wdog@5b004000 { compatible = "silabs,gecko-wdog"; reg = <0x5b004000 0x2C>; peripheral-id = <0>; interrupts = <42 0>; status = "disabled"; }; wdog1: wdog@5b008000 { compatible = "silabs,gecko-wdog"; reg = <0x5b008000 0x2C>; peripheral-id = <1>; interrupts = <43 0>; status = "disabled"; }; adc0: adc@59004000 { compatible = "silabs,gecko-iadc"; reg = <0x59004000 0x4000>; interrupts = <49 0>; status = "disabled"; #io-channel-cells = <1>; }; }; }; / { pinctrl: pin-controller { /* Pin controller is a "virtual" device since SiLabs SoCs do pin * control in a distributed way (GPIO registers and PSEL * registers on each peripheral). */ compatible = "silabs,gecko-pinctrl"; }; hwinfo: hwinfo { compatible = "silabs,gecko-hwinfo"; status = "disabled"; }; }; &nvic { arm,num-irq-priority-bits = <4>; };