44 	static unsigned int ver;  in zynqmp_get_silicon_ver()  local
46 	if (!ver) {  in zynqmp_get_silicon_ver()
47 		ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +  in zynqmp_get_silicon_ver()
49 		ver &= ZYNQMP_SILICON_VER_MASK;  in zynqmp_get_silicon_ver()
50 		ver >>= ZYNQMP_SILICON_VER_SHIFT;  in zynqmp_get_silicon_ver()
53 	return ver;  in zynqmp_get_silicon_ver()
58 	unsigned int ver = zynqmp_get_silicon_ver();  in get_uart_clk()  local
60 	if (ver == ZYNQMP_CSU_VERSION_QEMU) {  in get_uart_clk()
71 	uint16_t ver;  member
80 		.ver = 0x2c,
89 		.ver = 0x2c,
99 		.ver = 0x100,
105 		.ver = 0x12c,
115 		.ver = 0x100,
121 		.ver = 0x12c,
131 		.ver = 0x100,
137 		.ver = 0x12c,
146 		.ver = 0x2c,
155 		.ver = 0x2c,
233 	uint32_t id, ver, chipid[2];  in zynqmp_get_silicon_idcode_name()  local
244 	ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT;  in zynqmp_get_silicon_idcode_name()
248 		    zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK)) {  in zynqmp_get_silicon_idcode_name()
268 	if ((ver & ZYNQMP_PL_STATUS_MASK) != 0U) {  in zynqmp_get_silicon_idcode_name()
284 	uint32_t ver;  in zynqmp_get_rtl_ver()  local
286 	ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);  in zynqmp_get_rtl_ver()
287 	ver &= ZYNQMP_RTL_VER_MASK;  in zynqmp_get_rtl_ver()
288 	ver >>= ZYNQMP_RTL_VER_SHIFT;  in zynqmp_get_rtl_ver()
290 	return ver;  in zynqmp_get_rtl_ver()
339 	uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);  in zynqmp_get_ps_ver()  local
341 	ver &= ZYNQMP_PS_VER_MASK;  in zynqmp_get_ps_ver()
342 	ver >>= ZYNQMP_PS_VER_SHIFT;  in zynqmp_get_ps_ver()
344 	return ver + 1U;  in zynqmp_get_ps_ver()
349 	uint32_t ver = zynqmp_get_silicon_ver();  in zynqmp_print_platform_name()  local
353 	switch (ver) {  in zynqmp_print_platform_name()
408 	uint32_t ver = zynqmp_get_silicon_ver();  in plat_get_syscnt_freq2()  local
410 	if (ver == ZYNQMP_CSU_VERSION_QEMU) {  in plat_get_syscnt_freq2()