Lines Matching defs:pmu_slpdata_s

97 struct pmu_slpdata_s {  struct
98 	uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS];
99 	uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS];
100 	uint32_t dmac0_qos[CPU_AXI_QOS_NUM_REGS];
101 	uint32_t dmac1_qos[CPU_AXI_QOS_NUM_REGS];
102 	uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS];
103 	uint32_t crypto0_qos[CPU_AXI_QOS_NUM_REGS];
104 	uint32_t crypto1_qos[CPU_AXI_QOS_NUM_REGS];
105 	uint32_t pmu_cm0_qos[CPU_AXI_QOS_NUM_REGS];
106 	uint32_t peri_cm1_qos[CPU_AXI_QOS_NUM_REGS];
107 	uint32_t gic_qos[CPU_AXI_QOS_NUM_REGS];
108 	uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS];
109 	uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS];
110 	uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS];
111 	uint32_t usb_otg0_qos[CPU_AXI_QOS_NUM_REGS];
112 	uint32_t usb_otg1_qos[CPU_AXI_QOS_NUM_REGS];
113 	uint32_t usb_host0_qos[CPU_AXI_QOS_NUM_REGS];
114 	uint32_t usb_host1_qos[CPU_AXI_QOS_NUM_REGS];
115 	uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS];
116 	uint32_t video_m0_qos[CPU_AXI_QOS_NUM_REGS];
117 	uint32_t video_m1_r_qos[CPU_AXI_QOS_NUM_REGS];
118 	uint32_t video_m1_w_qos[CPU_AXI_QOS_NUM_REGS];
119 	uint32_t rga_r_qos[CPU_AXI_QOS_NUM_REGS];
120 	uint32_t rga_w_qos[CPU_AXI_QOS_NUM_REGS];
121 	uint32_t vop_big_r[CPU_AXI_QOS_NUM_REGS];
122 	uint32_t vop_big_w[CPU_AXI_QOS_NUM_REGS];
123 	uint32_t vop_little[CPU_AXI_QOS_NUM_REGS];
124 	uint32_t iep_qos[CPU_AXI_QOS_NUM_REGS];
125 	uint32_t isp1_m0_qos[CPU_AXI_QOS_NUM_REGS];
126 	uint32_t isp1_m1_qos[CPU_AXI_QOS_NUM_REGS];
127 	uint32_t isp0_m0_qos[CPU_AXI_QOS_NUM_REGS];
128 	uint32_t isp0_m1_qos[CPU_AXI_QOS_NUM_REGS];
129 	uint32_t hdcp_qos[CPU_AXI_QOS_NUM_REGS];
130 	uint32_t perihp_nsp_qos[CPU_AXI_QOS_NUM_REGS];
131 	uint32_t perilp_nsp_qos[CPU_AXI_QOS_NUM_REGS];
132 	uint32_t perilpslv_nsp_qos[CPU_AXI_QOS_NUM_REGS];
133 	uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS];