185 		struct rk3399_sdram_params *sdram_params,  in data_training()  argument
189 	uint32_t rank = sdram_params->ch[ch].rank;  in data_training()
193 	if (sdram_params->dramtype == LPDDR4)  in data_training()
202 		if (sdram_params->dramtype == LPDDR4) {  in data_training()
207 		} else if (sdram_params->dramtype == LPDDR3) {  in data_training()
210 		} else if (sdram_params->dramtype == DDR3) {  in data_training()
430 		struct rk3399_sdram_params *sdram_params,  in set_ddrconfig()  argument
434 	struct rk3399_sdram_channel *ch = &sdram_params->ch[channel];  in set_ddrconfig()
453 		struct rk3399_sdram_params *sdram_params)  in dram_all_config()  argument
458 		struct rk3399_sdram_channel *info = &sdram_params->ch[i];  in dram_all_config()
461 		if (sdram_params->ch[i].col == 0)  in dram_all_config()
475 		if (sdram_params->ch[i].rank == 1)  in dram_all_config()
479 	DDR_STRIDE(sdram_params->stride);  in dram_all_config()
490 		struct rk3399_sdram_params *sdram_params)  in pctl_cfg()  argument
492 	const uint32_t *params_ctl = sdram_params->pctl_regs.denali_ctl;  in pctl_cfg()
493 	const uint32_t *params_pi = sdram_params->pi_regs.denali_pi;  in pctl_cfg()
494 	const struct rk3399_ddr_publ_regs *phy_regs = &sdram_params->phy_regs;  in pctl_cfg()
547 		struct rk3399_sdram_params *sdram_params)  in dram_switch_to_next_index()  argument
562 	ch_count = sdram_params->num_channels;  in dram_switch_to_next_index()
570 		if (sdram_params->dramtype != LPDDR4) {  in dram_switch_to_next_index()
576 		if (data_training(ch, sdram_params, PI_FULL_TRAINING))  in dram_switch_to_next_index()
588 		struct rk3399_sdram_params *sdram_params)  in pctl_start()  argument
628 					   sdram_params->rx_cal_dqs[0][byte]);  in pctl_start()
647 					   sdram_params->rx_cal_dqs[1][byte]);  in pctl_start()
696 	struct rk3399_sdram_params *sdram_params = &sdram_config;  in dmc_suspend()  local
703 	phy_regs = &sdram_params->phy_regs;  in dmc_suspend()
704 	params_ctl = sdram_params->pctl_regs.denali_ctl;  in dmc_suspend()
705 	params_pi = sdram_params->pi_regs.denali_pi;  in dmc_suspend()
717 	sdram_params->ddr_freq = ((fbdiv * 24) /  in dmc_suspend()
720 	INFO("sdram_params->ddr_freq = %d\n", sdram_params->ddr_freq);  in dmc_suspend()
721 	sdram_params->odt = (((mmio_read_32(PHY_REG(0, 5)) >> 16) &  in dmc_suspend()
745 	for (ch = 0; ch < sdram_params->num_channels; ch++) {  in dmc_suspend()
747 			sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) &  in dmc_suspend()
785 	struct rk3399_sdram_params *sdram_params = &sdram_config;  in dmc_resume()  local
811 	for (channel = 0; channel < sdram_params->num_channels; channel++) {  in dmc_resume()
817 		if (sdram_params->dramtype == LPDDR4) {  in dmc_resume()
818 			phy_dll_bypass_set(channel, sdram_params->ddr_freq);  in dmc_resume()
820 		pctl_cfg(channel, sdram_params);  in dmc_resume()
824 		if (sdram_params->ch[channel].col)  in dmc_resume()
828 	if (pctl_start(channel_mask, sdram_params) < 0)  in dmc_resume()
831 	for (channel = 0; channel < sdram_params->num_channels; channel++) {  in dmc_resume()
833 		if (sdram_params->dramtype == LPDDR3)  in dmc_resume()
840 		if (sdram_params->dramtype != LPDDR4 &&  in dmc_resume()
841 		    data_training(channel, sdram_params, PI_FULL_TRAINING))  in dmc_resume()
844 		set_ddrconfig(sdram_params, channel,  in dmc_resume()
845 			      sdram_params->ch[channel].ddrconfig);  in dmc_resume()
848 	dram_all_config(sdram_params);  in dmc_resume()
851 	dram_switch_to_next_index(sdram_params);  in dmc_resume()