Lines Matching refs:cwl
233 pdram_timing->cwl = 6; in ddr3_get_parameter()
236 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; in ddr3_get_parameter()
268 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); in ddr3_get_parameter()
348 pdram_timing->todton = pdram_timing->cwl - 2; in ddr3_get_parameter()
438 pdram_timing->cwl = 2; in lpddr2_get_parameter()
442 pdram_timing->cwl = 2; in lpddr2_get_parameter()
446 pdram_timing->cwl = 3; in lpddr2_get_parameter()
450 pdram_timing->cwl = 4; in lpddr2_get_parameter()
454 pdram_timing->cwl = 4; in lpddr2_get_parameter()
680 pdram_timing->cwl = 3; in lpddr3_get_parameter()
684 pdram_timing->cwl = 4; in lpddr3_get_parameter()
688 pdram_timing->cwl = 5; in lpddr3_get_parameter()
692 pdram_timing->cwl = 6; in lpddr3_get_parameter()
696 pdram_timing->cwl = 6; in lpddr3_get_parameter()
700 pdram_timing->cwl = 6; in lpddr3_get_parameter()
704 pdram_timing->cwl = 8; in lpddr3_get_parameter()
708 pdram_timing->cwl = 8; in lpddr3_get_parameter()
985 pdram_timing->cwl = 4; in lpddr4_get_parameter()
997 pdram_timing->cwl = 6; in lpddr4_get_parameter()
1009 pdram_timing->cwl = 8; in lpddr4_get_parameter()
1021 pdram_timing->cwl = 10; in lpddr4_get_parameter()
1035 pdram_timing->cwl = 12; in lpddr4_get_parameter()
1049 pdram_timing->cwl = 14; in lpddr4_get_parameter()
1063 pdram_timing->cwl = 16; in lpddr4_get_parameter()
1077 pdram_timing->cwl = 18; in lpddr4_get_parameter()