44 	struct timing_related_config timing_config;  member
361 			     struct timing_related_config *timing_config)  in get_pi_wrlat()  argument
365 	if (timing_config->dram_type == LPDDR3) {  in get_pi_wrlat()
387 				 struct timing_related_config *timing_config)  in get_pi_wrlat_adj()  argument
389 	return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1;  in get_pi_wrlat_adj()
393 			struct timing_related_config *timing_config)  in get_pi_tdfi_phy_rdlat()  argument
421 	if (timing_config->dram_type == DDR3) {  in get_pi_tdfi_phy_rdlat()
423 	} else if (timing_config->dram_type == LPDDR4) {  in get_pi_tdfi_phy_rdlat()
425 	} else if (timing_config->dram_type == LPDDR3) {  in get_pi_tdfi_phy_rdlat()
450 				   struct timing_related_config *timing_config)  in get_pi_todtoff_min()  argument
454 	if (timing_config->dram_type == LPDDR3)  in get_pi_todtoff_min()
456 	else if (timing_config->dram_type == LPDDR4)  in get_pi_todtoff_min()
468 				   struct timing_related_config *timing_config)  in get_pi_todtoff_max()  argument
472 	if ((timing_config->dram_type == LPDDR4)  in get_pi_todtoff_max()
473 	    || (timing_config->dram_type == LPDDR3))  in get_pi_todtoff_max()
486 				     *timing_config,  in gen_rk3399_ctl_params_f0()
492 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_ctl_params_f0()
493 		if (timing_config->dram_type == DDR3) {  in gen_rk3399_ctl_params_f0()
494 			tmp = ((700000 + 10) * timing_config->freq +  in gen_rk3399_ctl_params_f0()
510 		} else if (timing_config->dram_type == LPDDR4) {  in gen_rk3399_ctl_params_f0()
589 				   (timing_config->dllbp << 24));  in gen_rk3399_ctl_params_f0()
615 		if (timing_config->dram_type == LPDDR4) {  in gen_rk3399_ctl_params_f0()
638 		if (timing_config->odt) {  in gen_rk3399_ctl_params_f0()
640 			if (timing_config->freq < 400)  in gen_rk3399_ctl_params_f0()
654 		    (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl)  in gen_rk3399_ctl_params_f0()
655 		     << 8) | get_rdlat_adj(timing_config->dram_type,  in gen_rk3399_ctl_params_f0()
664 		if ((timing_config->dram_type == LPDDR3) ||  in gen_rk3399_ctl_params_f0()
665 		    (timing_config->dram_type == LPDDR4)) {  in gen_rk3399_ctl_params_f0()
666 			tmp = get_pi_wrlat(pdram_timing, timing_config);  in gen_rk3399_ctl_params_f0()
667 			tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_ctl_params_f0()
675 		if ((timing_config->dram_type == LPDDR3) ||  in gen_rk3399_ctl_params_f0()
676 		    (timing_config->dram_type == LPDDR4)) {  in gen_rk3399_ctl_params_f0()
679 			    get_pi_todtoff_min(pdram_timing, timing_config) - 1;  in gen_rk3399_ctl_params_f0()
681 			tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_ctl_params_f0()
691 							  timing_config) &  in gen_rk3399_ctl_params_f0()
714 		tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config);  in gen_rk3399_ctl_params_f0()
715 		if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) {  in gen_rk3399_ctl_params_f0()
728 		if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) &&  in gen_rk3399_ctl_params_f0()
738 				     *timing_config,  in gen_rk3399_ctl_params_f1()
744 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_ctl_params_f1()
745 		if (timing_config->dram_type == DDR3) {  in gen_rk3399_ctl_params_f1()
747 			    ((700000 + 10) * timing_config->freq + 999) / 1000;  in gen_rk3399_ctl_params_f1()
760 		} else if (timing_config->dram_type == LPDDR4) {  in gen_rk3399_ctl_params_f1()
839 				   (timing_config->dllbp << 25));  in gen_rk3399_ctl_params_f1()
862 		if (timing_config->dram_type == LPDDR4) {  in gen_rk3399_ctl_params_f1()
887 		if (timing_config->odt) {  in gen_rk3399_ctl_params_f1()
889 			if (timing_config->freq < 400)  in gen_rk3399_ctl_params_f1()
902 				   (get_wrlat_adj(timing_config->dram_type,  in gen_rk3399_ctl_params_f1()
904 				   get_rdlat_adj(timing_config->dram_type,  in gen_rk3399_ctl_params_f1()
913 		if ((timing_config->dram_type == LPDDR3) ||  in gen_rk3399_ctl_params_f1()
914 		    (timing_config->dram_type == LPDDR4)) {  in gen_rk3399_ctl_params_f1()
915 			tmp = get_pi_wrlat(pdram_timing, timing_config);  in gen_rk3399_ctl_params_f1()
916 			tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_ctl_params_f1()
924 		if ((timing_config->dram_type == LPDDR3) ||  in gen_rk3399_ctl_params_f1()
925 		    (timing_config->dram_type == LPDDR4)) {  in gen_rk3399_ctl_params_f1()
928 			      get_pi_todtoff_min(pdram_timing, timing_config);  in gen_rk3399_ctl_params_f1()
931 			tmp1 = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_ctl_params_f1()
941 							  timing_config) &  in gen_rk3399_ctl_params_f1()
964 		tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config);  in gen_rk3399_ctl_params_f1()
965 		if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) {  in gen_rk3399_ctl_params_f1()
979 		if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) &&  in gen_rk3399_ctl_params_f1()
1015 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config,  in gen_rk3399_ctl_params()  argument
1020 		gen_rk3399_ctl_params_f0(timing_config, pdram_timing);  in gen_rk3399_ctl_params()
1022 		gen_rk3399_ctl_params_f1(timing_config, pdram_timing);  in gen_rk3399_ctl_params()
1025 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,  in gen_rk3399_pi_params_f0()  argument
1031 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_pi_params_f0()
1042 		if (timing_config->dram_type == LPDDR4)  in gen_rk3399_pi_params_f0()
1048 		      get_pi_tdfi_phy_rdlat(pdram_timing, timing_config);  in gen_rk3399_pi_params_f0()
1051 		if (timing_config->dram_type == LPDDR3) {  in gen_rk3399_pi_params_f0()
1052 			tmp = get_pi_wrlat(pdram_timing, timing_config);  in gen_rk3399_pi_params_f0()
1068 		if (timing_config->dram_type == LPDDR3) {  in gen_rk3399_pi_params_f0()
1069 			tmp = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_pi_params_f0()
1074 		if ((timing_config->dram_type == LPDDR3) ||  in gen_rk3399_pi_params_f0()
1075 		    (timing_config->dram_type == LPDDR4)) {  in gen_rk3399_pi_params_f0()
1076 			tmp1 = get_pi_wrlat(pdram_timing, timing_config);  in gen_rk3399_pi_params_f0()
1077 			tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_pi_params_f0()
1082 		} else if (timing_config->dram_type == DDR3) {  in gen_rk3399_pi_params_f0()
1087 		if ((timing_config->dram_type == LPDDR3) ||  in gen_rk3399_pi_params_f0()
1088 		    (timing_config->dram_type == LPDDR4)) {  in gen_rk3399_pi_params_f0()
1091 			tmp1 += get_pi_todtoff_min(pdram_timing, timing_config);  in gen_rk3399_pi_params_f0()
1094 			tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_pi_params_f0()
1099 		} else if (timing_config->dram_type == DDR3) {  in gen_rk3399_pi_params_f0()
1107 		tmp = get_pi_wrlat_adj(pdram_timing, timing_config);  in gen_rk3399_pi_params_f0()
1203 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,  in gen_rk3399_pi_params_f1()  argument
1209 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_pi_params_f1()
1220 		if (timing_config->dram_type == LPDDR4)  in gen_rk3399_pi_params_f1()
1226 		      get_pi_tdfi_phy_rdlat(pdram_timing, timing_config);  in gen_rk3399_pi_params_f1()
1229 		if (timing_config->dram_type == LPDDR3) {  in gen_rk3399_pi_params_f1()
1230 			tmp = get_pi_wrlat(pdram_timing, timing_config);  in gen_rk3399_pi_params_f1()
1245 		if (timing_config->dram_type == LPDDR3) {  in gen_rk3399_pi_params_f1()
1246 			tmp = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_pi_params_f1()
1250 		if ((timing_config->dram_type == LPDDR3) ||  in gen_rk3399_pi_params_f1()
1251 		    (timing_config->dram_type == LPDDR4)) {  in gen_rk3399_pi_params_f1()
1252 			tmp1 = get_pi_wrlat(pdram_timing, timing_config);  in gen_rk3399_pi_params_f1()
1253 			tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_pi_params_f1()
1258 		} else if (timing_config->dram_type == DDR3) {  in gen_rk3399_pi_params_f1()
1263 		if ((timing_config->dram_type == LPDDR3) ||  in gen_rk3399_pi_params_f1()
1264 		    (timing_config->dram_type == LPDDR4)) {  in gen_rk3399_pi_params_f1()
1267 			       get_pi_todtoff_min(pdram_timing, timing_config);  in gen_rk3399_pi_params_f1()
1270 			tmp2 = get_pi_todtoff_max(pdram_timing, timing_config);  in gen_rk3399_pi_params_f1()
1275 		} else if (timing_config->dram_type == DDR3)  in gen_rk3399_pi_params_f1()
1283 		tmp = get_pi_wrlat_adj(pdram_timing, timing_config);  in gen_rk3399_pi_params_f1()
1383 static void gen_rk3399_pi_params(struct timing_related_config *timing_config,  in gen_rk3399_pi_params()  argument
1388 		gen_rk3399_pi_params_f0(timing_config, pdram_timing);  in gen_rk3399_pi_params()
1390 		gen_rk3399_pi_params_f1(timing_config, pdram_timing);  in gen_rk3399_pi_params()
1398 	for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) {  in gen_rk3399_set_odt()
1500 static void gen_rk3399_phy_params(struct timing_related_config *timing_config,  in gen_rk3399_phy_params()  argument
1511 	for (i = 0; i < timing_config->ch_cnt; i++) {  in gen_rk3399_phy_params()
1521 		if (timing_config->freq > 400)  in gen_rk3399_phy_params()
1571 		if (timing_config->dram_type == DDR3) {  in gen_rk3399_phy_params()
1574 		} else if (timing_config->dram_type == LPDDR4) {  in gen_rk3399_phy_params()
1577 		} else if (timing_config->dram_type == LPDDR3) {  in gen_rk3399_phy_params()
1689 					  timing_config->dram_type);  in gen_rk3399_phy_params()
1806 	uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt;  in dram_low_power_config()
1807 	uint32_t dram_type = rk3399_dram_status.timing_config.dram_type;  in dram_low_power_config()
1842 	sdram_timing_cfg_init(&rk3399_dram_status.timing_config,  in dram_dfs_init()
1853 	if (rk3399_dram_status.timing_config.dram_type == DDR3) {  in dram_dfs_init()
1921 	dram_type = rk3399_dram_status.timing_config.dram_type;  in dram_set_odt_pd()
1922 	ch_count = rk3399_dram_status.timing_config.ch_cnt;  in dram_set_odt_pd()
1930 	rk3399_dram_status.timing_config.odt = arg2 & 0x1;  in dram_set_odt_pd()
1947 		if (rk3399_dram_status.timing_config.ch_cnt == 2)  in dram_set_odt_pd()
1985 	rk3399_dram_status.timing_config.freq = mhz;  in prepare_ddr_timing()
1988 		rk3399_dram_status.timing_config.dllbp = 1;  in prepare_ddr_timing()
1990 		rk3399_dram_status.timing_config.dllbp = 0;  in prepare_ddr_timing()
1992 	if (rk3399_dram_status.timing_config.odt == 1)  in prepare_ddr_timing()
2001 	dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing);  in prepare_ddr_timing()
2002 	gen_rk3399_ctl_params(&rk3399_dram_status.timing_config,  in prepare_ddr_timing()
2004 	gen_rk3399_pi_params(&rk3399_dram_status.timing_config,  in prepare_ddr_timing()
2006 	gen_rk3399_phy_params(&rk3399_dram_status.timing_config,  in prepare_ddr_timing()
2027 	gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt,  in ddr_set_rate()
2041 	if (rk3399_dram_status.timing_config.odt == 0)  in ddr_set_rate()
2048 	gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt);  in ddr_set_rate()
2075 	rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt;  in ddr_prepare_for_sys_suspend()
2077 	rk3399_dram_status.timing_config.odt = 1;  in ddr_prepare_for_sys_suspend()
2100 	rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt;  in ddr_prepare_for_sys_resume()
2112 	gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt);  in ddr_prepare_for_sys_resume()