Lines Matching refs:sram_data
29 static __sramdata struct rk3328_sleep_sram_data sram_data; variable
305 sram_data.dpll_con_save[i] = in dpll_suspend()
322 sram_data.dpll_con_save[1] | 0xc0000000); in dpll_resume()
471 sram_data.pmic_sleep_save = mmio_read_32(GRF_BASE + PMIC_SLEEP_REG); in rk3328_pmic_suspend()
472 sram_data.pmic_sleep_gpio_save[1] = mmio_read_32(GPIO2_BASE + 4); in rk3328_pmic_suspend()
473 sram_data.pmic_sleep_gpio_save[0] = mmio_read_32(GPIO2_BASE); in rk3328_pmic_suspend()
476 sram_data.pmic_sleep_gpio_save[1] | BIT(26)); in rk3328_pmic_suspend()
478 sram_data.pmic_sleep_gpio_save[0] | BIT(26)); in rk3328_pmic_suspend()
483 mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]); in rk3328_pmic_resume()
484 mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]); in rk3328_pmic_resume()
486 sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0)); in rk3328_pmic_resume()
493 sram_data.pd_sr_idle_save = mmio_read_32(DDR_UPCTL_BASE + in ddr_suspend()
495 sram_data.pd_sr_idle_save &= SELFREF_EN; in ddr_suspend()
498 sram_data.ddr_grf_con0 = mmio_read_32(DDR_GRF_BASE + in ddr_suspend()
551 mmio_write_32(DDR_GRF_BASE, sram_data.ddr_grf_con0 | 0xc0000000); in dmc_restore()
552 if (sram_data.pd_sr_idle_save) in dmc_restore()
559 sram_data.uart2_ier = mmio_read_32(UART2_BASE + UART_IER); in sram_dbg_uart_suspend()
571 mmio_write_32(UART2_BASE + UART_IER, sram_data.uart2_ier); in sram_dbg_uart_resume()