Lines Matching refs:PMU_BASE
40 pd_reg = mmio_read_32(PMU_BASE + PMU_PWRDN_CON) & BIT(cpu_id); in get_cpus_pwr_domain_cfg_info()
41 apm_reg = mmio_read_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id)) & in get_cpus_pwr_domain_cfg_info()
63 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
68 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
79 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
98 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
106 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
179 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_on_finish()
188 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()
509 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(0)); in ddr_suspend()
514 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(2)); in ddr_suspend()
544 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(2)); in dmc_restore()
546 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(0)); in dmc_restore()
581 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(PD_CPU0), apm_value); in sram_soc_enter_lp()
666 __func__, mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); in plat_rockchip_pmu_init()