126 	return mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd) ?  in pmu_power_domain_st()
138 	mmio_write_32(PMU_BASE + PMU_PWRDN_CON,  in pmu_power_domain_ctr()
159 	return !!((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & BIT(bus)) &&  in pmu_bus_idle_st()
160 		  (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & BIT(bus + 16)));  in pmu_bus_idle_st()
167 	mmio_write_32(PMU_BASE + PMU_BUS_IDLE_REQ,  in pmu_bus_idle_req()
178 		     __func__, mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), bus);  in pmu_bus_idle_req()
325 	pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST);  in pmu_power_domains_suspend()
396 		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),  in cpus_power_domain_on()
399 			mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),  in cpus_power_domain_on()
419 		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),  in cpus_power_domain_on()
438 		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),  in cpus_power_domain_off()
447 		mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),  in cpus_power_domain_off()
487 	mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),  in rockchip_soc_cores_pwr_dm_on_finish()
521 	mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id),  in rockchip_soc_cores_pwr_dm_resume()
709 			mmio_read_32(PMU_BASE + PMU_PWRMODE_CORE_LO);  in pmu_sleep_config()
711 			mmio_read_32(PMU_BASE + PMU_PWRMODE_CORE_HI);  in pmu_sleep_config()
713 			mmio_read_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_LO);  in pmu_sleep_config()
715 			mmio_read_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_HI);  in pmu_sleep_config()
716 	ddr_data.pmu_wkup_cfg2_l = mmio_read_32(PMU_BASE + PMU_WKUP_CFG2_LO);  in pmu_sleep_config()
758 	mmio_write_32(PMU_BASE + PMU_OSC_CNT_LO,  in pmu_sleep_config()
760 	mmio_write_32(PMU_BASE + PMU_OSC_CNT_HI,  in pmu_sleep_config()
763 	mmio_write_32(PMU_BASE + PMU_STABLE_CNT_LO,  in pmu_sleep_config()
765 	mmio_write_32(PMU_BASE + PMU_STABLE_CNT_HI,  in pmu_sleep_config()
768 	mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_LO,  in pmu_sleep_config()
770 	mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_HI,  in pmu_sleep_config()
777 	mmio_write_32(PMU_BASE + PMU_SCU_PWRDN_CNT_LO,  in pmu_sleep_config()
779 	mmio_write_32(PMU_BASE + PMU_SCU_PWRDN_CNT_HI,  in pmu_sleep_config()
782 	mmio_write_32(PMU_BASE + PMU_SCU_PWRUP_CNT_LO,  in pmu_sleep_config()
784 	mmio_write_32(PMU_BASE + PMU_SCU_PWRUP_CNT_HI,  in pmu_sleep_config()
787 	mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT_LO,  in pmu_sleep_config()
789 	mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT_HI,  in pmu_sleep_config()
792 	mmio_write_32(PMU_BASE + PMU_PLLRST_CNT_LO,  in pmu_sleep_config()
794 	mmio_write_32(PMU_BASE + PMU_PLLRST_CNT_HI,  in pmu_sleep_config()
798 	mmio_write_32(PMU_BASE + PMU_PWRMODE_CORE_LO,  in pmu_sleep_config()
800 	mmio_write_32(PMU_BASE + PMU_PWRMODE_CORE_HI,  in pmu_sleep_config()
803 	mmio_write_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_LO,  in pmu_sleep_config()
805 	mmio_write_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_HI,  in pmu_sleep_config()
808 	mmio_write_32(PMU_BASE + PMU_WKUP_CFG2_LO,  in pmu_sleep_config()
814 	mmio_write_32(PMU_BASE + PMU_PWRMODE_CORE_LO,  in pmu_sleep_restore()
816 	mmio_write_32(PMU_BASE + PMU_PWRMODE_CORE_HI,  in pmu_sleep_restore()
818 	mmio_write_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_LO,  in pmu_sleep_restore()
820 	mmio_write_32(PMU_BASE + PMU_PWRMODE_COMMON_CON_HI,  in pmu_sleep_restore()
822 	mmio_write_32(PMU_BASE + PMU_WKUP_CFG2_LO,  in pmu_sleep_restore()
1070 	     __func__, mmio_read_32(PMU_BASE + PMU_PWRDN_ST));  in plat_rockchip_pmu_init()