584 		mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_CON0);  in pvtm_32k_config()
586 		mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_CON1);  in pvtm_32k_config()
588 	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,  in pvtm_32k_config()
591 	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,  in pvtm_32k_config()
594 	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON1, PVTM_CALC_CNT);  in pvtm_32k_config()
597 	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,  in pvtm_32k_config()
604 	while (mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST1) < 30)  in pvtm_32k_config()
608 	while (!(mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST0) & 0x1))  in pvtm_32k_config()
612 		(mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST1) * 24000 +  in pvtm_32k_config()
625 	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,  in pvtm_32k_config()
638 	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0,  in pvtm_32k_config_restore()
640 	mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON1,  in pvtm_32k_config_restore()
668 		mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(0));  in ddr_sleep_config()
669 	mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(0),  in ddr_sleep_config()
676 	mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(0),  in ddr_sleep_config_restore()
706 	ddr_data.pmic_slp_iomux = mmio_read_32(PMUGRF_BASE + GPIO0A_IOMUX);  in pmu_sleep_config()
753 	mmio_write_32(PMUGRF_BASE + GPIO0A_IOMUX,  in pmu_sleep_config()
826 	mmio_write_32(PMUGRF_BASE + GPIO0A_IOMUX,  in pmu_sleep_restore()
832 	ddr_data.gpio0c_iomux = mmio_read_32(PMUGRF_BASE + GPIO0C_IOMUX);  in soc_sleep_config()
851 	mmio_write_32(PMUGRF_BASE + GPIO0C_IOMUX,  in soc_sleep_restore()
1022 	mmio_write_32(PMUGRF_BASE + GPIO0A_IOMUX, BITS_WITH_WMASK(0, 0x3, 8));  in rockchip_soc_system_off()