Lines Matching refs:w0
47 ldr w0, [x1, #SDRAM_CFG]
48 orr w0, w0, #SDRAM_CFG_MEM_HLT
49 str w0, [x1, #SDRAM_CFG]
51 ldr w0, [x1, #DEBUG_2]
52 and w0, w0, #DDR_DBG_2_MEM_IDLE
53 cbz w0, 2b
55 ldr w0, [x1, #DEBUG_26]
56 orr w0, w0, #DDR_DEBUG_26_BIT_12
57 orr w0, w0, #DDR_DEBUG_26_BIT_13
58 orr w0, w0, #DDR_DEBUG_26_BIT_14
62 orr w0, w0, #DDR_DEBUG_26_BIT_15
63 orr w0, w0, #DDR_DEBUG_26_BIT_16
64 str w0, [x1, #DEBUG_26]
66 ldr w0, [x1, #SDRAM_CFG_2]
67 orr w0, w0, #SDRAM_CFG2_FRC_SR
68 str w0, [x1, #SDRAM_CFG_2]
71 ldr w0, [x1, #DDR_DSR2]
72 orr w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
73 str w0, [x1, #DDR_DSR2]
74 ldr w0, [x1, #DDR_DSR2]
75 and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
76 cbnz w0, 3b
78 ldr w0, [x1, #SDRAM_INTERVAL]
79 and w0, w0, #SDRAM_INTERVAL_REFINT_CLEAR
80 str w0, [x1, #SDRAM_INTERVAL]
84 ldr w0, [x1, #SDRAM_MD_CNTL]
85 orr w0, w0, #MD_CNTL_CKE(1)
86 orr w0, w0, #MD_CNTL_MD_EN
87 str w0, [x1, #SDRAM_MD_CNTL]
89 ldr w0, [x1, #TIMING_CFG_10]
90 orr w0, w0, #DDR_TIMING_CFG_10_T_STAB
91 str w0, [x1, #TIMING_CFG_10]
93 ldr w0, [x1, #SDRAM_CFG_2]
94 and w0, w0, #SDRAM_CFG2_FRC_SR_CLEAR
95 str w0, [x1, #SDRAM_CFG_2]
98 ldr w0, [x1, #DDR_DSR2]
99 and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
100 cbz w0, 4b
105 ldr w0, [x1, #DEBUG_26]
106 orr w0, w0, #DDR_DEBUG_26_BIT_25
107 and w0, w0, #DDR_DEBUG_26_BIT_24_CLEAR
108 str w0, [x1, #DEBUG_26]
127 ldr w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
133 orr w0, w0, #(1 << NXP_LPGPR_ZEROTH_BIT)
136 str w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
152 ldr w0, [x1, #FSPI_IPCMD]
153 orr w0, w0, #FSPI_IPCMD_TRG_MASK
154 str w0, [x1, #FSPI_IPCMD]
156 ldr w0, [x1, #FSPI_INTR]
157 and w0, w0, #FSPI_INTR_IPCMDDONE_MASK
158 cmp w0, #0
161 ldr w0, [x1, #FSPI_IPTXFCR]
162 orr w0, w0, #FSPI_IPTXFCR_CLR
163 str w0, [x1, #FSPI_IPTXFCR]
165 ldr w0, [x1, #FSPI_INTR]
166 orr w0, w0, #FSPI_INTR_IPCMDDONE_MASK
167 str w0, [x1, #FSPI_INTR]
202 mov w0, #0x00000000
203 str w0, [x2, #RSTCNTL_OFFSET]
206 mov w0, #SW_RST_REQ_INIT
207 str w0, [x2, #RSTCNTL_OFFSET]