Lines Matching refs:pwrctrl
139 void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, in __spm_src_req_update() argument
143 1 : pwrctrl->reg_spm_apsrc_req; in __spm_src_req_update()
145 1 : pwrctrl->reg_spm_ddr_en_req; in __spm_src_req_update()
147 1 : pwrctrl->reg_spm_vrf18_req; in __spm_src_req_update()
149 1 : pwrctrl->reg_spm_infra_req; in __spm_src_req_update()
152 1 : pwrctrl->reg_spm_f26m_req; in __spm_src_req_update()
160 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | in __spm_src_req_update()
161 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | in __spm_src_req_update()
162 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | in __spm_src_req_update()
163 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | in __spm_src_req_update()
164 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); in __spm_src_req_update()
167 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl) in __spm_set_power_control() argument
173 ((pwrctrl->reg_wfi_op & 0x1) << 0) | in __spm_set_power_control()
174 ((pwrctrl->reg_wfi_type & 0x1) << 1) | in __spm_set_power_control()
175 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | in __spm_set_power_control()
176 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | in __spm_set_power_control()
177 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | in __spm_set_power_control()
178 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | in __spm_set_power_control()
179 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | in __spm_set_power_control()
180 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); in __spm_set_power_control()
184 ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) | in __spm_set_power_control()
185 ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) | in __spm_set_power_control()
186 ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) | in __spm_set_power_control()
187 ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) | in __spm_set_power_control()
188 ((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4)); in __spm_set_power_control()
192 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | in __spm_set_power_control()
193 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | in __spm_set_power_control()
194 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | in __spm_set_power_control()
195 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | in __spm_set_power_control()
196 ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) | in __spm_set_power_control()
197 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | in __spm_set_power_control()
198 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | in __spm_set_power_control()
199 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | in __spm_set_power_control()
200 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | in __spm_set_power_control()
201 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); in __spm_set_power_control()
205 ((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) | in __spm_set_power_control()
206 ((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) | in __spm_set_power_control()
207 ((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) | in __spm_set_power_control()
208 ((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) | in __spm_set_power_control()
209 ((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) | in __spm_set_power_control()
210 ((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) | in __spm_set_power_control()
211 ((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) | in __spm_set_power_control()
212 ((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) | in __spm_set_power_control()
213 ((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) | in __spm_set_power_control()
214 ((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) | in __spm_set_power_control()
215 ((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) | in __spm_set_power_control()
216 ((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) | in __spm_set_power_control()
217 ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | in __spm_set_power_control()
218 ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | in __spm_set_power_control()
219 ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) | in __spm_set_power_control()
220 ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) | in __spm_set_power_control()
221 ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) | in __spm_set_power_control()
222 ((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) | in __spm_set_power_control()
223 ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) | in __spm_set_power_control()
224 ((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) | in __spm_set_power_control()
225 ((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) | in __spm_set_power_control()
226 ((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) | in __spm_set_power_control()
227 ((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) | in __spm_set_power_control()
228 ((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) | in __spm_set_power_control()
229 ((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) | in __spm_set_power_control()
230 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) | in __spm_set_power_control()
231 ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) | in __spm_set_power_control()
232 ((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) | in __spm_set_power_control()
233 ((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) | in __spm_set_power_control()
234 ((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) | in __spm_set_power_control()
235 ((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) | in __spm_set_power_control()
236 ((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31)); in __spm_set_power_control()
240 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) | in __spm_set_power_control()
241 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) | in __spm_set_power_control()
242 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) | in __spm_set_power_control()
243 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) | in __spm_set_power_control()
244 ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) | in __spm_set_power_control()
245 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) | in __spm_set_power_control()
246 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) | in __spm_set_power_control()
247 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | in __spm_set_power_control()
248 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) | in __spm_set_power_control()
249 ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) | in __spm_set_power_control()
250 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) | in __spm_set_power_control()
251 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | in __spm_set_power_control()
252 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) | in __spm_set_power_control()
253 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) | in __spm_set_power_control()
254 ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) | in __spm_set_power_control()
255 ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) | in __spm_set_power_control()
256 ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) | in __spm_set_power_control()
257 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) | in __spm_set_power_control()
258 ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) | in __spm_set_power_control()
259 ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) | in __spm_set_power_control()
260 ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) | in __spm_set_power_control()
261 ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) | in __spm_set_power_control()
262 ((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) | in __spm_set_power_control()
263 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) | in __spm_set_power_control()
264 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) | in __spm_set_power_control()
265 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) | in __spm_set_power_control()
266 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) | in __spm_set_power_control()
267 ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) | in __spm_set_power_control()
268 ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) | in __spm_set_power_control()
269 ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) | in __spm_set_power_control()
270 ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) | in __spm_set_power_control()
271 ((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31)); in __spm_set_power_control()
275 ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) | in __spm_set_power_control()
276 ((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) | in __spm_set_power_control()
277 ((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) | in __spm_set_power_control()
278 ((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) | in __spm_set_power_control()
279 ((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) | in __spm_set_power_control()
280 ((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) | in __spm_set_power_control()
281 ((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) | in __spm_set_power_control()
282 ((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) | in __spm_set_power_control()
283 ((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) | in __spm_set_power_control()
284 ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) | in __spm_set_power_control()
285 ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) | in __spm_set_power_control()
286 ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) | in __spm_set_power_control()
287 ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) | in __spm_set_power_control()
288 ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) | in __spm_set_power_control()
289 ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) | in __spm_set_power_control()
290 ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) | in __spm_set_power_control()
291 ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) | in __spm_set_power_control()
292 ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) | in __spm_set_power_control()
293 ((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) | in __spm_set_power_control()
294 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) | in __spm_set_power_control()
295 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) | in __spm_set_power_control()
296 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) | in __spm_set_power_control()
297 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) | in __spm_set_power_control()
298 ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) | in __spm_set_power_control()
299 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) | in __spm_set_power_control()
300 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) | in __spm_set_power_control()
301 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) | in __spm_set_power_control()
302 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) | in __spm_set_power_control()
303 ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31)); in __spm_set_power_control()
307 ((pwrctrl->ccif_event_mask_b & 0xffff) << 0) | in __spm_set_power_control()
308 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) | in __spm_set_power_control()
309 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) | in __spm_set_power_control()
310 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) | in __spm_set_power_control()
311 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) | in __spm_set_power_control()
312 ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) | in __spm_set_power_control()
313 ((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) | in __spm_set_power_control()
314 ((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) | in __spm_set_power_control()
315 ((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) | in __spm_set_power_control()
316 ((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) | in __spm_set_power_control()
317 ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) | in __spm_set_power_control()
318 ((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) | in __spm_set_power_control()
319 ((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27)); in __spm_set_power_control()
323 ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) | in __spm_set_power_control()
324 ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) | in __spm_set_power_control()
325 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) | in __spm_set_power_control()
326 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) | in __spm_set_power_control()
327 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) | in __spm_set_power_control()
328 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) | in __spm_set_power_control()
329 ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) | in __spm_set_power_control()
330 ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) | in __spm_set_power_control()
331 ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) | in __spm_set_power_control()
332 ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) | in __spm_set_power_control()
333 ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) | in __spm_set_power_control()
334 ((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27)); in __spm_set_power_control()
338 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); in __spm_set_power_control()
342 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); in __spm_set_power_control()
352 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) in __spm_set_wakeup_event() argument
363 if (pwrctrl->timer_val_cust == 0U) { in __spm_set_wakeup_event()
364 val = pwrctrl->timer_val; in __spm_set_wakeup_event()
366 val = pwrctrl->timer_val_cust; in __spm_set_wakeup_event()
373 if (pwrctrl->wake_src_cust == 0U) { in __spm_set_wakeup_event()
374 mask = pwrctrl->wake_src; in __spm_set_wakeup_event()
376 mask = pwrctrl->wake_src_cust; in __spm_set_wakeup_event()
379 if (pwrctrl->reg_csyspwrreq_mask != 0U) { in __spm_set_wakeup_event()
395 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) in __spm_set_pcm_flags() argument
398 if (pwrctrl->pcm_flags_cust_clr != 0U) { in __spm_set_pcm_flags()
399 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; in __spm_set_pcm_flags()
402 if (pwrctrl->pcm_flags_cust_set != 0U) { in __spm_set_pcm_flags()
403 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set; in __spm_set_pcm_flags()
406 if (pwrctrl->pcm_flags1_cust_clr != 0U) { in __spm_set_pcm_flags()
407 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; in __spm_set_pcm_flags()
410 if (pwrctrl->pcm_flags1_cust_set != 0U) { in __spm_set_pcm_flags()
411 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; in __spm_set_pcm_flags()
414 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags); in __spm_set_pcm_flags()
415 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1); in __spm_set_pcm_flags()
416 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags); in __spm_set_pcm_flags()
417 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1); in __spm_set_pcm_flags()