131 void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,  in __spm_src_req_update()  argument
135 			     1 : pwrctrl->reg_spm_apsrc_req;  in __spm_src_req_update()
137 			     1 : pwrctrl->reg_spm_ddren_req;  in __spm_src_req_update()
139 			     1 : pwrctrl->reg_spm_vrf18_req;  in __spm_src_req_update()
141 			     1 : pwrctrl->reg_spm_infra_req;  in __spm_src_req_update()
143 			     1 : pwrctrl->reg_spm_f26m_req;  in __spm_src_req_update()
150 		(pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)  in __spm_src_req_update()
151 		 ? 0U : pwrctrl->reg_sspm_srcclkena_mask_b;  in __spm_src_req_update()
154 		(pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)  in __spm_src_req_update()
155 		 ? 0 : pwrctrl->reg_sspm_infra_req_mask_b;  in __spm_src_req_update()
164 		      ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |  in __spm_src_req_update()
165 		      ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |  in __spm_src_req_update()
166 		      ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |  in __spm_src_req_update()
167 		      ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |  in __spm_src_req_update()
168 		      ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));  in __spm_src_req_update()
172 		      ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |  in __spm_src_req_update()
173 		      ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |  in __spm_src_req_update()
174 		      ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |  in __spm_src_req_update()
175 		      ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |  in __spm_src_req_update()
176 		      ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |  in __spm_src_req_update()
177 		      ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |  in __spm_src_req_update()
178 		      ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |  in __spm_src_req_update()
179 		      ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |  in __spm_src_req_update()
180 		      ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |  in __spm_src_req_update()
181 		      ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |  in __spm_src_req_update()
182 		      ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |  in __spm_src_req_update()
183 		      ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |  in __spm_src_req_update()
184 		      ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |  in __spm_src_req_update()
185 		      ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |  in __spm_src_req_update()
186 		      ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |  in __spm_src_req_update()
187 		      ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |  in __spm_src_req_update()
188 		      ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |  in __spm_src_req_update()
189 		      ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |  in __spm_src_req_update()
190 		      ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |  in __spm_src_req_update()
191 		      ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |  in __spm_src_req_update()
192 		      ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |  in __spm_src_req_update()
195 		      ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |  in __spm_src_req_update()
196 		      ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |  in __spm_src_req_update()
197 		      ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));  in __spm_src_req_update()
200 void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)  in __spm_set_power_control()  argument
206 		      ((pwrctrl->reg_wfi_op & 0x1) << 0) |  in __spm_set_power_control()
207 		      ((pwrctrl->reg_wfi_type & 0x1) << 1) |  in __spm_set_power_control()
208 		      ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |  in __spm_set_power_control()
209 		      ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |  in __spm_set_power_control()
210 		      ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |  in __spm_set_power_control()
211 		      ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |  in __spm_set_power_control()
212 		      ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |  in __spm_set_power_control()
213 		      ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));  in __spm_set_power_control()
217 		      ((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) |  in __spm_set_power_control()
218 		      ((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16));  in __spm_set_power_control()
222 		      ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |  in __spm_set_power_control()
223 		      ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |  in __spm_set_power_control()
224 		      ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |  in __spm_set_power_control()
225 		      ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |  in __spm_set_power_control()
226 		      ((pwrctrl->reg_spm_ddren_req & 0x1) << 7) |  in __spm_set_power_control()
227 		      ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |  in __spm_set_power_control()
228 		      ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |  in __spm_set_power_control()
229 		      ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |  in __spm_set_power_control()
230 		      ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |  in __spm_set_power_control()
231 		      ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));  in __spm_set_power_control()
235 		      ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |  in __spm_set_power_control()
236 		      ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
237 		      ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
238 		      ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |  in __spm_set_power_control()
239 		      ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |  in __spm_set_power_control()
240 		      ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |  in __spm_set_power_control()
241 		      ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |  in __spm_set_power_control()
242 		      ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |  in __spm_set_power_control()
243 		      ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |  in __spm_set_power_control()
244 		      ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |  in __spm_set_power_control()
245 		      ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |  in __spm_set_power_control()
246 		      ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |  in __spm_set_power_control()
247 		      ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |  in __spm_set_power_control()
248 		      ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |  in __spm_set_power_control()
249 		      ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |  in __spm_set_power_control()
250 		      ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
251 		      ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |  in __spm_set_power_control()
252 		      ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |  in __spm_set_power_control()
253 		      ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |  in __spm_set_power_control()
254 		      ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
255 		      ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
256 		      ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) |  in __spm_set_power_control()
257 		      ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) |  in __spm_set_power_control()
258 		      ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |  in __spm_set_power_control()
259 		      ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |  in __spm_set_power_control()
260 		      ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));  in __spm_set_power_control()
264 		((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |  in __spm_set_power_control()
265 		((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
266 		((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
267 		((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |  in __spm_set_power_control()
268 		((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) |  in __spm_set_power_control()
269 		((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |  in __spm_set_power_control()
270 		((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |  in __spm_set_power_control()
271 		((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |  in __spm_set_power_control()
272 		((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |  in __spm_set_power_control()
273 		((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) |  in __spm_set_power_control()
274 		((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |  in __spm_set_power_control()
275 		((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |  in __spm_set_power_control()
276 		((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |  in __spm_set_power_control()
277 		((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |  in __spm_set_power_control()
278 		((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) |  in __spm_set_power_control()
279 		((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
280 		((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) |  in __spm_set_power_control()
281 		((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |  in __spm_set_power_control()
282 		((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) |  in __spm_set_power_control()
283 		((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
284 		((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
285 		((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |  in __spm_set_power_control()
286 		((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) |  in __spm_set_power_control()
287 		((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |  in __spm_set_power_control()
288 		((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |  in __spm_set_power_control()
289 		((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
290 		((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
291 		((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) |  in __spm_set_power_control()
292 		((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |  in __spm_set_power_control()
293 		((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |  in __spm_set_power_control()
294 		((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |  in __spm_set_power_control()
295 		((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31));  in __spm_set_power_control()
299 		((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |  in __spm_set_power_control()
300 		((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) |  in __spm_set_power_control()
301 		((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) |  in __spm_set_power_control()
302 		((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) |  in __spm_set_power_control()
303 		((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) |  in __spm_set_power_control()
304 		((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) |  in __spm_set_power_control()
305 		((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) |  in __spm_set_power_control()
306 		((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) |  in __spm_set_power_control()
307 		((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) |  in __spm_set_power_control()
308 		((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) |  in __spm_set_power_control()
309 		((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) |  in __spm_set_power_control()
310 		((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |  in __spm_set_power_control()
311 		((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |  in __spm_set_power_control()
312 		((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
313 		((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
314 		((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) |  in __spm_set_power_control()
315 		((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |  in __spm_set_power_control()
316 		((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |  in __spm_set_power_control()
317 		((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |  in __spm_set_power_control()
318 		((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
319 		((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
320 		((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |  in __spm_set_power_control()
321 		((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |  in __spm_set_power_control()
322 		((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |  in __spm_set_power_control()
323 		((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |  in __spm_set_power_control()
324 		((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31));  in __spm_set_power_control()
328 		((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) |  in __spm_set_power_control()
329 		((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |  in __spm_set_power_control()
330 		((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |  in __spm_set_power_control()
331 		((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |  in __spm_set_power_control()
332 		((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
333 		((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
334 		((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) |  in __spm_set_power_control()
335 		((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) |  in __spm_set_power_control()
336 		((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |  in __spm_set_power_control()
337 		((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26));  in __spm_set_power_control()
341 		((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |  in __spm_set_power_control()
342 		((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) |  in __spm_set_power_control()
343 		((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) |  in __spm_set_power_control()
344 		((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) |  in __spm_set_power_control()
345 		((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) |  in __spm_set_power_control()
346 		((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) |  in __spm_set_power_control()
347 		((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) |  in __spm_set_power_control()
348 		((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) |  in __spm_set_power_control()
349 		((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) |  in __spm_set_power_control()
350 		((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) |  in __spm_set_power_control()
351 		((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) |  in __spm_set_power_control()
352 		((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27));  in __spm_set_power_control()
356 		((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));  in __spm_set_power_control()
360 		((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));  in __spm_set_power_control()
364 		((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) |  in __spm_set_power_control()
365 		((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) |  in __spm_set_power_control()
366 		((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) |  in __spm_set_power_control()
367 		((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) |  in __spm_set_power_control()
368 		((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) |  in __spm_set_power_control()
369 		((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) |  in __spm_set_power_control()
370 		((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) |  in __spm_set_power_control()
371 		((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) |  in __spm_set_power_control()
372 		((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) |  in __spm_set_power_control()
373 		((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9));  in __spm_set_power_control()
383 void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)  in __spm_set_wakeup_event()  argument
394 	if (pwrctrl->timer_val_cust == 0U) {  in __spm_set_wakeup_event()
395 		val = pwrctrl->timer_val ? (pwrctrl->timer_val) : (PCM_TIMER_MAX);  in __spm_set_wakeup_event()
397 		val = pwrctrl->timer_val_cust;  in __spm_set_wakeup_event()
404 	if (pwrctrl->wake_src_cust == 0U) {  in __spm_set_wakeup_event()
405 		mask = pwrctrl->wake_src;  in __spm_set_wakeup_event()
407 		mask = pwrctrl->wake_src_cust;  in __spm_set_wakeup_event()
410 	if (pwrctrl->reg_csyspwrup_ack_mask != 0U) {  in __spm_set_wakeup_event()
426 void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)  in __spm_set_pcm_flags()  argument
429 	if (pwrctrl->pcm_flags_cust_clr != 0U) {  in __spm_set_pcm_flags()
430 		pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;  in __spm_set_pcm_flags()
433 	if (pwrctrl->pcm_flags_cust_set != 0U) {  in __spm_set_pcm_flags()
434 		pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;  in __spm_set_pcm_flags()
437 	if (pwrctrl->pcm_flags1_cust_clr != 0U) {  in __spm_set_pcm_flags()
438 		pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;  in __spm_set_pcm_flags()
441 	if (pwrctrl->pcm_flags1_cust_set != 0U) {  in __spm_set_pcm_flags()
442 		pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;  in __spm_set_pcm_flags()
445 	mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);  in __spm_set_pcm_flags()
447 	mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);  in __spm_set_pcm_flags()
449 	mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);  in __spm_set_pcm_flags()
451 	mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);  in __spm_set_pcm_flags()