15 #define DRAM_CH0_MMAP_LOW_REG(iface, cs, base)	\  argument
16 	(base + DRAM_CH0_MMAP_LOW_OFFSET + (iface) * 0x10000 + (cs) * 0x8)
17 #define DRAM_CH0_MMAP_HIGH_REG(iface, cs, base)	\  argument
18 	(DRAM_CH0_MMAP_LOW_REG(iface, cs, base) + 4)
29 #define DRAM_CS_ENABLED(iface, cs, base) \  argument
30 	(mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \
32 #define GET_DRAM_REGION_SIZE_CODE(iface, cs, base) \  argument
33 	(mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \
81 	uint8_t cs, iface;  in mvebu_get_dram_size()  local
83 	for (iface = 0; iface < DRAM_MAX_IFACE; iface++) {  in mvebu_get_dram_size()
87 			if (!DRAM_CS_ENABLED(iface, cs, ap_base_addr))  in mvebu_get_dram_size()
94 				GET_DRAM_REGION_SIZE_CODE(iface, cs,  in mvebu_get_dram_size()