Lines Matching refs:status
156 int status = INTEL_SIP_SMC_STATUS_OK; in intel_fpga_config_completed_write() local
162 status = mailbox_read_response(job_id, in intel_fpga_config_completed_write()
165 if (status < 0) { in intel_fpga_config_completed_write()
180 if (status != MBOX_NO_RESPONSE && in intel_fpga_config_completed_write()
181 status != MBOX_TIMEOUT && resp_len != 0) { in intel_fpga_config_completed_write()
193 status = INTEL_SIP_SMC_STATUS_OK; in intel_fpga_config_completed_write()
195 status = INTEL_SIP_SMC_STATUS_BUSY; in intel_fpga_config_completed_write()
209 return status; in intel_fpga_config_completed_write()
216 int status = 0; in intel_fpga_config_start() local
237 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, in intel_fpga_config_start()
240 if (status < 0) { in intel_fpga_config_start()
553 int status; local
557 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
560 if (status < 0) {
585 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, local
588 if (status < 0) {
589 *mbox_status = -status;
603 int status; local
606 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
609 if (status < 0) {
620 int status = 0; local
632 status = mailbox_read_response_async(job_id,
635 status = mailbox_read_response(job_id,
638 if (status == MBOX_NO_RESPONSE) {
639 status = MBOX_BUSY;
643 if (status == MBOX_NO_RESPONSE) {
647 if (status == MBOX_BUSY) {
654 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 ||
655 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) {
656 *mbox_error = -status;
657 } else if (status != MBOX_RET_OK) {
658 *mbox_error = -status;
668 int status = 0; local
672 status = socfpga_bridges_enable((uint32_t)mask);
674 status = socfpga_bridges_enable(~0);
678 status = socfpga_bridges_disable((uint32_t)mask);
680 status = socfpga_bridges_disable(~0);
684 if (status < 0) {
718 int status = INTEL_SIP_SMC_STATUS_OK; local
729 status = intel_mailbox_fpga_config_isdone();
730 SMC_RET4(handle, status, 0, 0, 0);
739 status = intel_fpga_config_start(x1);
740 SMC_RET4(handle, status, 0, 0, 0);
743 status = intel_fpga_config_write(x1, x2);
744 SMC_RET4(handle, status, 0, 0, 0);
747 status = intel_fpga_config_completed_write(completed_addr,
766 SMC_RET4(handle, status, 0, 0, 0);
774 status = intel_secure_reg_read(x1, &retval);
775 SMC_RET3(handle, status, retval, x1);
778 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
779 SMC_RET3(handle, status, retval, x1);
782 status = intel_secure_reg_update(x1, (uint32_t)x2,
784 SMC_RET3(handle, status, retval, x1);
787 status = intel_rsu_status(rsu_respbuf,
789 if (status) {
790 SMC_RET1(handle, status);
797 status = intel_rsu_update(x1);
798 SMC_RET1(handle, status);
801 status = intel_rsu_notify(x1);
802 SMC_RET1(handle, status);
805 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
807 if (status) {
808 SMC_RET1(handle, status);
810 SMC_RET2(handle, status, retval);
819 status = intel_rsu_copy_dcmf_version(x1, x2);
820 SMC_RET1(handle, status);
830 status = intel_rsu_copy_dcmf_status(x1);
831 SMC_RET1(handle, status);
841 status = intel_ecc_dbe_notification(x1);
842 SMC_RET1(handle, status);
845 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
847 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
850 status = intel_smc_fw_version(&retval);
851 SMC_RET2(handle, status, retval);
856 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
858 SMC_RET3(handle, status, mbox_status, len_in_resp);
861 status = intel_smc_get_usercode(&retval);
862 SMC_RET2(handle, status, retval);
868 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
870 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
872 status = INTEL_SIP_SMC_STATUS_REJECTED;
875 SMC_RET3(handle, status, x4, x5);
883 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6,
886 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6,
889 status = INTEL_SIP_SMC_STATUS_REJECTED;
892 SMC_RET4(handle, status, mbox_error, x6, x7);
895 status = intel_fcs_random_number_gen(x1, &retval64,
897 SMC_RET4(handle, status, mbox_error, x1, retval64);
900 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
902 SMC_RET1(handle, status);
905 status = intel_fcs_send_cert(x1, x2, &send_id);
906 SMC_RET1(handle, status);
909 status = intel_fcs_get_provision_data(&send_id);
910 SMC_RET1(handle, status);
913 status = intel_fcs_cntr_set_preauth(x1, x2, x3,
915 SMC_RET2(handle, status, mbox_error);
918 status = intel_hps_set_bridges(x1, x2);
919 SMC_RET1(handle, status);
922 status = intel_hwmon_readtemp(x1, &retval);
923 SMC_RET2(handle, status, retval);
926 status = intel_hwmon_readvolt(x1, &retval);
927 SMC_RET2(handle, status, retval);
930 status = intel_fcs_sigma_teardown(x1, &mbox_error);
931 SMC_RET2(handle, status, mbox_error);
934 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
935 SMC_RET4(handle, status, mbox_error, retval, retval2);
938 status = intel_fcs_attestation_subkey(x1, x2, x3,
940 SMC_RET4(handle, status, mbox_error, x3, x4);
943 status = intel_fcs_get_measurement(x1, x2, x3,
945 SMC_RET4(handle, status, mbox_error, x3, x4);
948 status = intel_fcs_get_attestation_cert(x1, x2,
950 SMC_RET4(handle, status, mbox_error, x2, x3);
953 status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
954 SMC_RET2(handle, status, mbox_error);
957 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
958 SMC_RET3(handle, status, mbox_error, retval);
961 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
962 SMC_RET2(handle, status, mbox_error);
965 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id);
966 SMC_RET1(handle, status);
969 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
971 SMC_RET4(handle, status, mbox_error, x3, x4);
974 status = intel_fcs_remove_crypto_service_key(x1, x2,
976 SMC_RET2(handle, status, mbox_error);
979 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
981 SMC_RET4(handle, status, mbox_error, x3, x4);
985 status = intel_fcs_get_digest_init(x1, x2, x3,
987 SMC_RET2(handle, status, mbox_error);
992 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
995 SMC_RET4(handle, status, mbox_error, x5, x6);
1000 status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
1003 SMC_RET4(handle, status, mbox_error, x5, x6);
1008 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1011 SMC_RET4(handle, status, mbox_error, x5, x6);
1016 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
1019 SMC_RET4(handle, status, mbox_error, x5, x6);
1023 status = intel_fcs_mac_verify_init(x1, x2, x3,
1025 SMC_RET2(handle, status, mbox_error);
1031 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1034 SMC_RET4(handle, status, mbox_error, x5, x6);
1040 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
1043 SMC_RET4(handle, status, mbox_error, x5, x6);
1049 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1052 SMC_RET4(handle, status, mbox_error, x5, x6);
1058 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
1061 SMC_RET4(handle, status, mbox_error, x5, x6);
1065 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
1067 SMC_RET2(handle, status, mbox_error);
1072 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1075 SMC_RET4(handle, status, mbox_error, x5, x6);
1080 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
1083 SMC_RET4(handle, status, mbox_error, x5, x6);
1088 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1091 SMC_RET4(handle, status, mbox_error, x5, x6);
1096 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
1099 SMC_RET4(handle, status, mbox_error, x5, x6);
1103 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
1105 SMC_RET2(handle, status, mbox_error);
1110 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
1112 SMC_RET4(handle, status, mbox_error, x5, x6);
1116 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
1118 SMC_RET2(handle, status, mbox_error);
1123 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
1125 SMC_RET4(handle, status, mbox_error, x5, x6);
1129 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
1131 SMC_RET2(handle, status, mbox_error);
1137 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1140 SMC_RET4(handle, status, mbox_error, x5, x6);
1146 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1149 SMC_RET4(handle, status, mbox_error, x5, x6);
1155 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
1158 SMC_RET4(handle, status, mbox_error, x5, x6);
1164 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1167 SMC_RET4(handle, status, mbox_error, x5, x6);
1171 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
1173 SMC_RET2(handle, status, mbox_error);
1176 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
1178 SMC_RET4(handle, status, mbox_error, x3, x4);
1182 status = intel_fcs_ecdh_request_init(x1, x2, x3,
1184 SMC_RET2(handle, status, mbox_error);
1189 status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
1191 SMC_RET4(handle, status, mbox_error, x5, x6);
1195 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
1197 SMC_RET2(handle, status, mbox_error);
1202 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1204 SMC_RET1(handle, status);
1209 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
1211 SMC_RET1(handle, status);
1214 status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
1216 SMC_RET4(handle, status, mbox_error, x1, retval64);
1224 status = intel_sdm_seu_err_read(seu_respbuf,
1226 if (status) {
1227 SMC_RET1(handle, status);