433 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)  argument
439 	*retval = mmio_read_32(reg_addr);
445 				uint32_t *retval)  argument
453 	return intel_secure_reg_read(reg_addr, retval);
457 				 uint32_t val, uint32_t *retval)  argument
459 	if (!intel_secure_reg_read(reg_addr, retval)) {
460 		*retval &= ~mask;
461 		*retval |= val & mask;
462 		return intel_secure_reg_write(reg_addr, *retval, retval);
532 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval)  argument
534 	if (mailbox_hwmon_readtemp(chan, retval) < 0) {
541 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval)  argument
543 	if (mailbox_hwmon_readvolt(chan, retval) < 0) {
714 	uint32_t retval = 0, completed_addr[3];  local
748 							&retval, &rcv_id);
749 		switch (retval) {
774 		status = intel_secure_reg_read(x1, &retval);
775 		SMC_RET3(handle, status, retval, x1);
778 		status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
779 		SMC_RET3(handle, status, retval, x1);
783 						 (uint32_t)x3, &retval);
784 		SMC_RET3(handle, status, retval, x1);
806 						ARRAY_SIZE(rsu_respbuf), &retval);
810 			SMC_RET2(handle, status, retval);
850 		status = intel_smc_fw_version(&retval);
851 		SMC_RET2(handle, status, retval);
861 		status = intel_smc_get_usercode(&retval);
862 		SMC_RET2(handle, status, retval);
922 		status = intel_hwmon_readtemp(x1, &retval);
923 		SMC_RET2(handle, status, retval);
926 		status = intel_hwmon_readvolt(x1, &retval);
927 		SMC_RET2(handle, status, retval);
934 		status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
935 		SMC_RET4(handle, status, mbox_error, retval, retval2);
957 		status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
958 		SMC_RET3(handle, status, mbox_error, retval);