100 	sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);  in lpuart32_serial_setbrg()
184 	err = sc_rm_get_partition(ipc_handle, &secure_part);  in mx8_partition_resources()
186 	err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false,  in mx8_partition_resources()
189 	err = sc_rm_set_parent(ipc_handle, os_part, secure_part);  in mx8_partition_resources()
193 		err = sc_rm_set_resource_movable(ipc_handle, secure_rsrcs[i],  in mx8_partition_resources()
200 	owned = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_0_PID0);  in mx8_partition_resources()
202 		err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0,  in mx8_partition_resources()
209 	owned2 = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_1_PID0);  in mx8_partition_resources()
211 		err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0,  in mx8_partition_resources()
218 	err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);  in mx8_partition_resources()
224 		err = sc_rm_set_peripheral_permissions(ipc_handle, ns_access_allowed[i],  in mx8_partition_resources()
232 		err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0,  in mx8_partition_resources()
237 		err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_0_PID0);  in mx8_partition_resources()
243 		err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0,  in mx8_partition_resources()
248 		err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_1_PID0);  in mx8_partition_resources()
261 		owned = sc_rm_is_memreg_owned(ipc_handle, mr);  in mx8_partition_resources()
263 			err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end);  in mx8_partition_resources()
270 				err = sc_rm_assign_memreg(ipc_handle, os_part, mr);  in mx8_partition_resources()
279 		err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end);  in mx8_partition_resources()
283 			err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end);  in mx8_partition_resources()
287 			err = sc_rm_assign_memreg(ipc_handle, os_part, mr);  in mx8_partition_resources()
294 			err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1);  in mx8_partition_resources()
298 			err = sc_rm_assign_memreg(ipc_handle, os_part, mr);  in mx8_partition_resources()
318 	if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE)  in bl31_early_platform_setup2()
322 	sc_pm_set_resource_power_mode(ipc_handle, IMX_RES_UART,  in bl31_early_platform_setup2()
325 	sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);  in bl31_early_platform_setup2()
326 	sc_pm_clock_enable(ipc_handle, IMX_RES_UART, 2, true, false);  in bl31_early_platform_setup2()
329 	sc_pad_set(ipc_handle, IMX_PAD_UART_RX, UART_PAD_CTRL);  in bl31_early_platform_setup2()
330 	sc_pad_set(ipc_handle, IMX_PAD_UART_TX, UART_PAD_CTRL);  in bl31_early_platform_setup2()
331 	sc_pad_set(ipc_handle, IMX_PAD_UART_RTS_B, UART_PAD_CTRL);  in bl31_early_platform_setup2()
332 	sc_pad_set(ipc_handle, IMX_PAD_UART_CTS_B, UART_PAD_CTRL);  in bl31_early_platform_setup2()
342 	sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON);  in bl31_early_platform_setup2()
344 	sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON);  in bl31_early_platform_setup2()
345 	sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0);  in bl31_early_platform_setup2()