32 	 unsigned int fsp_index)  in lpddr4_swffc()  argument
46 	mr = mr_data[fsp_index][0];  in lpddr4_swffc()
47 	emr  = mr_data[fsp_index][1];  in lpddr4_swffc()
48 	emr2 = mr_data[fsp_index][2];  in lpddr4_swffc()
49 	emr3 = mr_data[fsp_index][3];  in lpddr4_swffc()
50 	mr11 = mr_data[fsp_index][4];  in lpddr4_swffc()
51 	mr12 = mr_data[fsp_index][5];  in lpddr4_swffc()
52 	mr22 = mr_data[fsp_index][6];  in lpddr4_swffc()
53 	mr14 = mr_data[fsp_index][7];  in lpddr4_swffc()
171 	mmio_write_32(DDRC_MSTR2(0), fsp_index);  in lpddr4_swffc()
188 	val |= (fsp_index << 8);  in lpddr4_swffc()
200 	dram_clock_switch(info->timing_info->fsp_table[fsp_index], info->bypass_mode);  in lpddr4_swffc()
211 	if (fsp_index == 0) {  in lpddr4_swffc()
213 	} else  if (fsp_index == 1) {  in lpddr4_swffc()
243 	if (fsp_index == 1)  in lpddr4_swffc()
245 	else if (fsp_index == 2)  in lpddr4_swffc()
280 	if (fsp_index == 1)  in lpddr4_swffc()
282 	else if (fsp_index == 2)  in lpddr4_swffc()