Lines Matching refs:l
59 l.movhi r13, 0x1f0 # address of R_CPUCFG (delay)
60 l.lwz r5, 0x1500(r13) # core output clamps
61 l.or r5, r5, r6 # set bit to ...
62 l.sw 0x1500(r13), r5 # ... activate for our core
64 1: l.lwz r5, 0x1c30(r13) # CPU power-on reset
65 l.xori r6, r6, -1 # negate core mask
66 l.and r5, r5, r6 # clear bit to ...
67 l.sw 0x1c30(r13), r5 # ... assert for our core
69 l.ff1 r6, r3 # get core number from high mask
70 l.addi r6, r6, -17 # convert to 0-3
71 l.slli r6, r6, 2 # r5: core number*4 (0-12)
72 l.add r6, r6, r13 # add to base address
73 l.ori r5, r0, 0xff # 0xff means all switches off
74 l.sw 0x1540(r6), r5 # core power switch registers
76 reset: l.sw 0x1c00(r13),r0 # pull down our own reset line
78 l.j reset # just in case ....
79 l.nop 0x0 # (delay slot)
83 l.movhi r3, 0 # FIXUP! with core mask
84 l.movhi r0, 0 # clear r0
85 l.movhi r13, 0x901 # r13: CPU_CFG_BASE=0x09010000
87 l.lwz r5, 0x80(r13) # load C_CPU_STATUS
88 l.and r5, r5, r3 # mask requested core
89 l.sfeq r5, r0 # is it not yet in WFI?
90 l.bf 1b # try again
92 l.srli r6, r3, 16 # move mask to lower 16 bits(ds)
93 l.sfeqi r6, 1 # core 0 is special
94 l.bf 1f # don't touch the bit for core 0