Lines Matching refs:r2
57 zeroreg1 .req r2 /* Source register filled with 0 */
153 cmp r2, #4
157 subs r2, r2, #4
165 subs r2, r2, #1
234 and r2, lr, r1
235 subs r0, r2, r6 /* Diff(S) = Current Address - Compiled Address */
240 ldr r2, =__GOT_END__
241 add r2, r2, r0
262 cmp r1, r2
268 ldr r2, =__RELA_END__
269 add r2, r2, r0
312 cmp r1, r2