Lines Matching defs:nand_param_page
97 struct nand_param_page { struct
99 uint32_t page_sig;
100 uint16_t rev;
101 uint16_t features;
102 uint16_t opt_cmd;
103 uint8_t jtg;
104 uint8_t train_cmd;
105 uint16_t ext_param_length;
106 uint8_t nb_param_pages;
107 uint8_t reserved1[17];
109 uint8_t manufacturer[12];
110 uint8_t model[20];
111 uint8_t manufacturer_id;
112 uint16_t data_code;
113 uint8_t reserved2[13];
115 uint32_t bytes_per_page;
116 uint16_t spare_per_page;
117 uint32_t bytes_per_partial;
118 uint16_t spare_per_partial;
119 uint32_t num_pages_per_blk;
120 uint32_t num_blk_in_lun;
121 uint8_t num_lun;
122 uint8_t num_addr_cycles;
123 uint8_t bit_per_cell;
124 uint16_t max_bb_per_lun;
125 uint16_t blk_endur;
126 uint8_t valid_blk_begin;
127 uint16_t blk_enbur_valid;
128 uint8_t nb_prog_page;
129 uint8_t partial_prog_attr;
130 uint8_t nb_ecc_bits;
131 uint8_t plane_addr;
132 uint8_t mplanes_ops;
133 uint8_t ez_nand;
134 uint8_t reserved3[12];
136 uint8_t io_pin_cap_max;
137 uint16_t sdr_timing_mode;
138 uint16_t sdr_prog_cache_timing;
139 uint16_t tprog;
140 uint16_t tbers;
141 uint16_t tr;
142 uint16_t tccs;
143 uint8_t nvddr_timing_mode;
144 uint8_t nvddr2_timing_mode;
145 uint8_t nvddr_features;
146 uint16_t clk_input_cap_typ;
147 uint16_t io_pin_cap_typ;
148 uint16_t input_pin_cap_typ;
149 uint8_t input_pin_cap_max;
150 uint8_t drv_strength_support;
151 uint16_t tr_max;
152 uint16_t tadl;
153 uint16_t tr_typ;
154 uint8_t reserved4[6];
156 uint16_t vendor_revision;
157 uint8_t vendor[88];
158 uint16_t crc16;