Lines Matching refs:rcc
84 clocks = <&rcc TIM12_K>;
93 clocks = <&rcc USART2_K>;
94 resets = <&rcc USART2_R>;
102 clocks = <&rcc USART3_K>;
103 resets = <&rcc USART3_R>;
111 clocks = <&rcc UART4_K>;
112 resets = <&rcc UART4_R>;
121 clocks = <&rcc UART5_K>;
122 resets = <&rcc UART5_R>;
132 clocks = <&rcc I2C2_K>;
133 resets = <&rcc I2C2_R>;
145 clocks = <&rcc UART7_K>;
146 resets = <&rcc UART7_R>;
154 clocks = <&rcc UART8_K>;
155 resets = <&rcc UART8_R>;
163 clocks = <&rcc USART6_K>;
164 resets = <&rcc USART6_R>;
173 clocks = <&rcc TIM15_K>;
181 clocks = <&rcc USBO_K>;
183 resets = <&rcc USBO_R>;
194 rcc: rcc@50000000 { label
195 compatible = "st,stm32mp1-rcc", "syscon";
209 st,tzcr = <&rcc 0x0 0x1>;
264 clocks = <&rcc SYSCFG>;
271 clocks = <&rcc HASH1>;
272 resets = <&rcc HASH1_R>;
279 clocks = <&rcc RNG1_K>;
280 resets = <&rcc RNG1_R>;
289 clocks = <&rcc FMC_K>;
290 resets = <&rcc FMC_R>;
319 clocks = <&rcc QSPI_K>;
320 resets = <&rcc QSPI_R>;
329 clocks = <&rcc SDMMC1_K>;
331 resets = <&rcc SDMMC1_R>;
343 clocks = <&rcc SDMMC2_K>;
345 resets = <&rcc SDMMC2_R>;
356 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
364 clocks = <&rcc AXIDCG>,
365 <&rcc DDRC1>,
366 <&rcc DDRC2>,
367 <&rcc DDRPHYC>,
368 <&rcc DDRCAPB>,
369 <&rcc DDRPHYCAPB>;
385 clocks = <&rcc USBPHY_K>;
386 resets = <&rcc USBPHY_R>;
406 clocks = <&rcc USART1_K>;
407 resets = <&rcc USART1_R>;
417 clocks = <&rcc SPI6_K>;
418 resets = <&rcc SPI6_R>;
428 clocks = <&rcc I2C4_K>;
429 resets = <&rcc I2C4_R>;
441 clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
449 clocks = <&rcc RTCAPB>, <&rcc RTC>;
500 clocks = <&rcc TZPC>;
514 clocks = <&rcc I2C6_K>;
515 resets = <&rcc I2C6_R>;
527 clocks = <&rcc RTCAPB>;
548 clocks = <&rcc GPIOA>;
559 clocks = <&rcc GPIOB>;
570 clocks = <&rcc GPIOC>;
581 clocks = <&rcc GPIOD>;
592 clocks = <&rcc GPIOE>;
603 clocks = <&rcc GPIOF>;
614 clocks = <&rcc GPIOG>;
625 clocks = <&rcc GPIOH>;
636 clocks = <&rcc GPIOI>;
647 clocks = <&rcc GPIOJ>;
658 clocks = <&rcc GPIOK>;
678 clocks = <&rcc GPIOZ>;