Lines Matching refs:rcc
22 clocks = <&rcc CK_MPU>;
85 clocks = <&rcc USART3_K>;
86 resets = <&rcc USART3_R>;
94 clocks = <&rcc UART4_K>;
95 resets = <&rcc UART4_R>;
103 clocks = <&rcc UART5_K>;
104 resets = <&rcc UART5_R>;
112 clocks = <&rcc UART7_K>;
113 resets = <&rcc UART7_R>;
121 clocks = <&rcc UART8_K>;
122 resets = <&rcc UART8_R>;
130 clocks = <&rcc USART6_K>;
131 resets = <&rcc USART6_R>;
138 clocks = <&rcc USBO_K>;
140 resets = <&rcc USBO_R>;
155 clocks = <&rcc USART1_K>;
156 resets = <&rcc USART1_R>;
164 clocks = <&rcc USART2_K>;
165 resets = <&rcc USART2_R>;
175 clocks = <&rcc I2C3_K>;
176 resets = <&rcc I2C3_R>;
190 clocks = <&rcc I2C4_K>;
191 resets = <&rcc I2C4_R>;
205 clocks = <&rcc I2C5_K>;
206 resets = <&rcc I2C5_R>;
214 rcc: rcc@50000000 { label
215 compatible = "st,stm32mp13-rcc", "syscon";
259 clocks = <&rcc SYSCFG>;
265 clocks = <&rcc HASH1>;
266 resets = <&rcc HASH1_R>;
273 clocks = <&rcc RNG1_K>;
274 resets = <&rcc RNG1_R>;
288 clocks = <&rcc FMC_K>;
289 resets = <&rcc FMC_R>;
312 clocks = <&rcc QSPI_K>;
313 resets = <&rcc QSPI_R>;
321 clocks = <&rcc SDMMC1_K>;
323 resets = <&rcc SDMMC1_R>;
334 clocks = <&rcc SDMMC2_K>;
336 resets = <&rcc SDMMC2_R>;
346 clocks = <&rcc USBH>;
347 resets = <&rcc USBH_R>;
355 clocks = <&rcc USBH>;
356 resets = <&rcc USBH_R>;
365 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
373 clocks = <&rcc AXIDCG>,
374 <&rcc DDRC1>,
375 <&rcc DDRPHYC>,
376 <&rcc DDRCAPB>,
377 <&rcc DDRPHYCAPB>;
391 clocks = <&rcc USBPHY_K>;
392 resets = <&rcc USBPHY_R>;
412 clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
479 clocks = <&rcc GPIOA>;
491 clocks = <&rcc GPIOB>;
503 clocks = <&rcc GPIOC>;
515 clocks = <&rcc GPIOD>;
527 clocks = <&rcc GPIOE>;
539 clocks = <&rcc GPIOF>;
551 clocks = <&rcc GPIOG>;
563 clocks = <&rcc GPIOH>;
575 clocks = <&rcc GPIOI>;