28 	ufshc_dme_set(VS_MPHY_DISABLE_OFFSET, 0, VS_MPHY_DISABLE_MPHYDIS);  in dwufs_phy_init()
29 	ufshc_dme_set(PA_HS_SERIES_OFFSET, 0, 2);  in dwufs_phy_init()
31 	ufshc_dme_set(0x8114, 0, 1);  in dwufs_phy_init()
33 	ufshc_dme_set(0x8121, 0, 0x2d);  in dwufs_phy_init()
35 	ufshc_dme_set(0x8122, 0, 0x1);  in dwufs_phy_init()
36 	ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);  in dwufs_phy_init()
39 	ufshc_dme_set(0x800d, 4, 0x58);  in dwufs_phy_init()
41 	ufshc_dme_set(0x800d, 5, 0x58);  in dwufs_phy_init()
43 	ufshc_dme_set(0x800e, 4, 0xb);  in dwufs_phy_init()
45 	ufshc_dme_set(0x800e, 5, 0xb);  in dwufs_phy_init()
47 	ufshc_dme_set(0x8009, 4, 0x1);  in dwufs_phy_init()
49 	ufshc_dme_set(0x8009, 5, 0x1);  in dwufs_phy_init()
50 	ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);  in dwufs_phy_init()
52 	ufshc_dme_set(0x8113, 0, 0x1);  in dwufs_phy_init()
53 	ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);  in dwufs_phy_init()
55 	ufshc_dme_set(RX_HS_G3_SYNC_LENGTH_CAP_OFFSET, 4, 0x4a);  in dwufs_phy_init()
56 	ufshc_dme_set(RX_HS_G3_SYNC_LENGTH_CAP_OFFSET, 5, 0x4a);  in dwufs_phy_init()
57 	ufshc_dme_set(RX_HS_G2_SYNC_LENGTH_CAP_OFFSET, 4, 0x4a);  in dwufs_phy_init()
58 	ufshc_dme_set(RX_HS_G2_SYNC_LENGTH_CAP_OFFSET, 5, 0x4a);  in dwufs_phy_init()
59 	ufshc_dme_set(RX_MIN_ACTIVATETIME_CAP_OFFSET, 4, 0x7);  in dwufs_phy_init()
60 	ufshc_dme_set(RX_MIN_ACTIVATETIME_CAP_OFFSET, 5, 0x7);  in dwufs_phy_init()
61 	ufshc_dme_set(TX_HIBERN8TIME_CAP_OFFSET, 0, 0x5);  in dwufs_phy_init()
62 	ufshc_dme_set(TX_HIBERN8TIME_CAP_OFFSET, 1, 0x5);  in dwufs_phy_init()
63 	ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1);  in dwufs_phy_init()
68 	ufshc_dme_set(VS_MPHY_DISABLE_OFFSET, 0, 0);  in dwufs_phy_init()
83 	ufshc_dme_set(PA_LOCAL_TX_LCC_ENABLE_OFFSET, 0, 0);  in dwufs_phy_init()
84 	ufshc_dme_set(VS_MK2_EXTN_SUPPORT_OFFSET, 0, 0);  in dwufs_phy_init()
89 	ufshc_dme_set(DL_AFC0_CREDIT_THRESHOLD_OFFSET, 0, 0);  in dwufs_phy_init()
90 	ufshc_dme_set(DL_TC0_OUT_ACK_THRESHOLD_OFFSET, 0, 0);  in dwufs_phy_init()
91 	ufshc_dme_set(DL_TC0_TX_FC_THRESHOLD_OFFSET, 0, 9);  in dwufs_phy_init()
110 		result = ufshc_dme_set(0xd0a0, 0x0, 0x10);  in dwufs_phy_set_pwr_mode()
113 		result = ufshc_dme_set(0x1556, 0x0, 0x48);  in dwufs_phy_set_pwr_mode()
120 		result = ufshc_dme_set(PA_TACTIVATE_OFFSET, 0, 7);  in dwufs_phy_set_pwr_mode()
128 	result = ufshc_dme_set(PA_TX_SKIP_OFFSET, 0, 0);  in dwufs_phy_set_pwr_mode()
130 	result = ufshc_dme_set(PA_TX_GEAR_OFFSET, 0, 3);  in dwufs_phy_set_pwr_mode()
132 	result = ufshc_dme_set(PA_RX_GEAR_OFFSET, 0, 3);  in dwufs_phy_set_pwr_mode()
134 	result = ufshc_dme_set(PA_HS_SERIES_OFFSET, 0, 2);  in dwufs_phy_set_pwr_mode()
136 	result = ufshc_dme_set(PA_TX_TERMINATION_OFFSET, 0, 1);  in dwufs_phy_set_pwr_mode()
138 	result = ufshc_dme_set(PA_RX_TERMINATION_OFFSET, 0, 1);  in dwufs_phy_set_pwr_mode()
140 	result = ufshc_dme_set(PA_SCRAMBLING_OFFSET, 0, 0);  in dwufs_phy_set_pwr_mode()
142 	result = ufshc_dme_set(PA_ACTIVE_TX_DATA_LANES_OFFSET, 0, tx_lanes);  in dwufs_phy_set_pwr_mode()
144 	result = ufshc_dme_set(PA_ACTIVE_RX_DATA_LANES_OFFSET, 0, rx_lanes);  in dwufs_phy_set_pwr_mode()
146 	result = ufshc_dme_set(PA_PWR_MODE_USER_DATA0_OFFSET, 0, 8191);  in dwufs_phy_set_pwr_mode()
148 	result = ufshc_dme_set(PA_PWR_MODE_USER_DATA1_OFFSET, 0, 65535);  in dwufs_phy_set_pwr_mode()
150 	result = ufshc_dme_set(PA_PWR_MODE_USER_DATA2_OFFSET, 0, 32767);  in dwufs_phy_set_pwr_mode()
152 	result = ufshc_dme_set(DME_FC0_PROTECTION_TIMEOUT_OFFSET, 0, 8191);  in dwufs_phy_set_pwr_mode()
154 	result = ufshc_dme_set(DME_TC0_REPLAY_TIMEOUT_OFFSET, 0, 65535);  in dwufs_phy_set_pwr_mode()
156 	result = ufshc_dme_set(DME_AFC0_REQ_TIMEOUT_OFFSET, 0, 32767);  in dwufs_phy_set_pwr_mode()
158 	result = ufshc_dme_set(PA_PWR_MODE_USER_DATA3_OFFSET, 0, 8191);  in dwufs_phy_set_pwr_mode()
160 	result = ufshc_dme_set(PA_PWR_MODE_USER_DATA4_OFFSET, 0, 65535);  in dwufs_phy_set_pwr_mode()
162 	result = ufshc_dme_set(PA_PWR_MODE_USER_DATA5_OFFSET, 0, 32767);  in dwufs_phy_set_pwr_mode()
164 	result = ufshc_dme_set(DME_FC1_PROTECTION_TIMEOUT_OFFSET, 0, 8191);  in dwufs_phy_set_pwr_mode()
166 	result = ufshc_dme_set(DME_TC1_REPLAY_TIMEOUT_OFFSET, 0, 65535);  in dwufs_phy_set_pwr_mode()
168 	result = ufshc_dme_set(DME_AFC1_REQ_TIMEOUT_OFFSET, 0, 32767);  in dwufs_phy_set_pwr_mode()
171 	result = ufshc_dme_set(PA_PWR_MODE_OFFSET, 0, 0x11);  in dwufs_phy_set_pwr_mode()