155 static struct stm32_fmc2_nfc stm32_fmc2;  variable
159 	return stm32_fmc2.reg_base;  in fmc2_base()
165 	unsigned long hclk = clk_get_rate(stm32_fmc2.clock_id);  in stm32_fmc2_nand_setup_timing()
570 	uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base;  in stm32_fmc2_read_data()
617 	uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base;  in stm32_fmc2_write_data()
707 		mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base,  in stm32_fmc2_exec()
712 		mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base,  in stm32_fmc2_exec()
779 	mmio_write_32(stm32_fmc2.reg_base + FMC2_PCR, pcr);  in stm32_fmc2_setup()
815 	stm32_fmc2.reg_base = info.base;  in stm32_fmc2_init()
821 	stm32_fmc2.clock_id = (unsigned long)info.clock;  in stm32_fmc2_init()
822 	stm32_fmc2.reset_id = (unsigned int)info.reset;  in stm32_fmc2_init()
865 		stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*(cuint + 1)) +  in stm32_fmc2_init()
872 		stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 4)) +  in stm32_fmc2_init()
879 		stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 7)) +  in stm32_fmc2_init()
903 		stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint);  in stm32_fmc2_init()
904 		if (stm32_fmc2.cs_sel >= MAX_CS) {  in stm32_fmc2_init()
908 		VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel);  in stm32_fmc2_init()
912 	clk_enable(stm32_fmc2.clock_id);  in stm32_fmc2_init()
915 	ret = stm32mp_reset_assert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS);  in stm32_fmc2_init()
919 	ret = stm32mp_reset_deassert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS);  in stm32_fmc2_init()