Lines Matching refs:priv

276 static void stm32mp1_wait_operating_mode(struct stm32mp_ddr_priv *priv, uint32_t mode)  in stm32mp1_wait_operating_mode()  argument
287 stat = mmio_read_32((uintptr_t)&priv->ctl->stat); in stm32mp1_wait_operating_mode()
291 (uintptr_t)&priv->ctl->stat, stat); in stm32mp1_wait_operating_mode()
321 (uintptr_t)&priv->ctl->stat, stat); in stm32mp1_wait_operating_mode()
325 static void stm32mp1_mode_register_write(struct stm32mp_ddr_priv *priv, uint8_t addr, in stm32mp1_mode_register_write() argument
338 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) & in stm32mp1_mode_register_write()
351 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
353 (uintptr_t)&priv->ctl->mrctrl0, in stm32mp1_mode_register_write()
354 mmio_read_32((uintptr_t)&priv->ctl->mrctrl0), mrctrl0); in stm32mp1_mode_register_write()
355 mmio_write_32((uintptr_t)&priv->ctl->mrctrl1, data); in stm32mp1_mode_register_write()
357 (uintptr_t)&priv->ctl->mrctrl1, in stm32mp1_mode_register_write()
358 mmio_read_32((uintptr_t)&priv->ctl->mrctrl1)); in stm32mp1_mode_register_write()
368 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
370 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) & in stm32mp1_mode_register_write()
376 (uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
380 static void stm32mp1_ddr3_dll_off(struct stm32mp_ddr_priv *priv) in stm32mp1_ddr3_dll_off() argument
382 uint32_t mr1 = mmio_read_32((uintptr_t)&priv->phy->mr1); in stm32mp1_ddr3_dll_off()
383 uint32_t mr2 = mmio_read_32((uintptr_t)&priv->phy->mr2); in stm32mp1_ddr3_dll_off()
393 mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF); in stm32mp1_ddr3_dll_off()
395 (uintptr_t)&priv->ctl->dbg1, in stm32mp1_ddr3_dll_off()
396 mmio_read_32((uintptr_t)&priv->ctl->dbg1)); in stm32mp1_ddr3_dll_off()
407 dbgcam = mmio_read_32((uintptr_t)&priv->ctl->dbgcam); in stm32mp1_ddr3_dll_off()
409 (uintptr_t)&priv->ctl->dbgcam, dbgcam); in stm32mp1_ddr3_dll_off()
421 stm32mp1_mode_register_write(priv, 1, mr1); in stm32mp1_ddr3_dll_off()
436 stm32mp1_mode_register_write(priv, 2, mr2); in stm32mp1_ddr3_dll_off()
446 stm32mp1_mode_register_write(priv, 1, mr1); in stm32mp1_ddr3_dll_off()
453 mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
456 (uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
457 mmio_read_32((uintptr_t)&priv->ctl->pwrctl)); in stm32mp1_ddr3_dll_off()
465 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_SR); in stm32mp1_ddr3_dll_off()
471 stm32mp_ddr_start_sw_done(priv->ctl); in stm32mp1_ddr3_dll_off()
473 mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE); in stm32mp1_ddr3_dll_off()
475 (uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr3_dll_off()
476 mmio_read_32((uintptr_t)&priv->ctl->mstr)); in stm32mp1_ddr3_dll_off()
478 stm32mp_ddr_wait_sw_done_ack(priv->ctl); in stm32mp1_ddr3_dll_off()
490 mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
493 mmio_setbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
497 mmio_setbits_32((uintptr_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS); in stm32mp1_ddr3_dll_off()
499 mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr, in stm32mp1_ddr3_dll_off()
501 mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr, in stm32mp1_ddr3_dll_off()
504 mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr, in stm32mp1_ddr3_dll_off()
506 mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr, in stm32mp1_ddr3_dll_off()
511 mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
513 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); in stm32mp1_ddr3_dll_off()
527 mmio_clrbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF); in stm32mp1_ddr3_dll_off()
529 (uintptr_t)&priv->ctl->dbg1, in stm32mp1_ddr3_dll_off()
530 mmio_read_32((uintptr_t)&priv->ctl->dbg1)); in stm32mp1_ddr3_dll_off()
562 void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, in stm32mp1_ddr_init() argument
594 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
595 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
596 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
597 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
598 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
599 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
602 if (stm32mp1_ddr_clk_enable(priv, config->info.speed) != 0) { in stm32mp1_ddr_init()
608 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
609 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
614 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
622 mmio_clrbits_32((uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
625 (uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
626 mmio_read_32((uintptr_t)&priv->ctl->dfimisc)); in stm32mp1_ddr_init()
628 stm32mp_ddr_set_reg(priv, REG_REG, &config->c_reg, ddr_registers); in stm32mp1_ddr_init()
635 mmio_clrbits_32((uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr_init()
638 (uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr_init()
639 mmio_read_32((uintptr_t)&priv->ctl->mstr)); in stm32mp1_ddr_init()
642 stm32mp_ddr_set_reg(priv, REG_TIMING, &config->c_timing, ddr_registers); in stm32mp1_ddr_init()
643 stm32mp_ddr_set_reg(priv, REG_MAP, &config->c_map, ddr_registers); in stm32mp1_ddr_init()
646 mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0, in stm32mp1_ddr_init()
650 (uintptr_t)&priv->ctl->init0, in stm32mp1_ddr_init()
651 mmio_read_32((uintptr_t)&priv->ctl->init0)); in stm32mp1_ddr_init()
653 stm32mp_ddr_set_reg(priv, REG_PERF, &config->c_perf, ddr_registers); in stm32mp1_ddr_init()
656 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
657 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
658 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
664 stm32mp_ddr_set_reg(priv, REGPHY_REG, &config->p_reg, ddr_registers); in stm32mp1_ddr_init()
665 stm32mp_ddr_set_reg(priv, REGPHY_TIMING, &config->p_timing, ddr_registers); in stm32mp1_ddr_init()
672 mmio_clrbits_32((uintptr_t)&priv->phy->mr1, BIT(0)); in stm32mp1_ddr_init()
674 (uintptr_t)&priv->phy->mr1, in stm32mp1_ddr_init()
675 mmio_read_32((uintptr_t)&priv->phy->mr1)); in stm32mp1_ddr_init()
682 stm32mp1_ddrphy_idone_wait(priv->phy); in stm32mp1_ddr_init()
697 stm32mp1_ddrphy_init(priv->phy, pir); in stm32mp1_ddr_init()
703 stm32mp_ddr_start_sw_done(priv->ctl); in stm32mp1_ddr_init()
705 mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
708 (uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
709 mmio_read_32((uintptr_t)&priv->ctl->dfimisc)); in stm32mp1_ddr_init()
711 stm32mp_ddr_wait_sw_done_ack(priv->ctl); in stm32mp1_ddr_init()
719 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); in stm32mp1_ddr_init()
723 stm32mp1_ddr3_dll_off(priv); in stm32mp1_ddr_init()
734 stm32mp1_refresh_disable(priv->ctl); in stm32mp1_ddr_init()
752 stm32mp1_ddrphy_init(priv->phy, pir); in stm32mp1_ddr_init()
755 stm32mp1_ddrphy_idone_wait(priv->phy); in stm32mp1_ddr_init()
760 stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, in stm32mp1_ddr_init()
763 stm32mp_ddr_enable_axi_port(priv->ctl); in stm32mp1_ddr_init()