679 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_rcc_is_secure()  local
682 	return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;  in stm32mp1_rcc_is_secure()
687 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_rcc_is_mckprot()  local
690 	return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;  in stm32mp1_rcc_is_mckprot()
744 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_clk_get_parent()  local
771 	p_sel = (mmio_read_32(rcc_base + sel->offset) &  in stm32mp1_clk_get_parent()
798 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_pll_get_fvco()  local
800 	cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);  in stm32mp1_pll_get_fvco()
801 	fracr = mmio_read_32(rcc_base + pll->pllxfracr);  in stm32mp1_pll_get_fvco()
853 	uintptr_t rcc_base = stm32mp_rcc_base();  in get_clock_rate()  local
858 		reg = mmio_read_32(rcc_base + RCC_MPCKSELR);  in get_clock_rate()
872 			reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);  in get_clock_rate()
886 		reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);  in get_clock_rate()
902 		reg = mmio_read_32(rcc_base + RCC_AXIDIVR);  in get_clock_rate()
907 			reg = mmio_read_32(rcc_base + RCC_APB4DIVR);  in get_clock_rate()
911 			reg = mmio_read_32(rcc_base + RCC_APB5DIVR);  in get_clock_rate()
923 		reg = mmio_read_32(rcc_base + RCC_MSSCKSELR);  in get_clock_rate()
942 		reg = mmio_read_32(rcc_base + RCC_MCUDIVR);  in get_clock_rate()
947 			reg = mmio_read_32(rcc_base + RCC_APB1DIVR);  in get_clock_rate()
951 			reg = mmio_read_32(rcc_base + RCC_APB2DIVR);  in get_clock_rate()
955 			reg = mmio_read_32(rcc_base + RCC_APB3DIVR);  in get_clock_rate()
964 		reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);  in get_clock_rate()
996 		clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U;  in get_clock_rate()
1054 	uintptr_t rcc_base = stm32mp_rcc_base();  in __clk_enable()  local
1059 		mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));  in __clk_enable()
1061 		mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));  in __clk_enable()
1067 	uintptr_t rcc_base = stm32mp_rcc_base();  in __clk_disable()  local
1072 		mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,  in __clk_disable()
1075 		mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));  in __clk_disable()
1081 	uintptr_t rcc_base = stm32mp_rcc_base();  in __clk_is_enabled()  local
1083 	return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);  in __clk_is_enabled()
1233 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp_clk_get_rate()  local
1254 		prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) &  in stm32mp_clk_get_rate()
1256 		timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) &  in stm32mp_clk_get_rate()
1265 		prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) &  in stm32mp_clk_get_rate()
1267 		timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) &  in stm32mp_clk_get_rate()
1328 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_lse_enable()  local
1331 		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);  in stm32mp1_lse_enable()
1335 		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);  in stm32mp1_lse_enable()
1342 	value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>  in stm32mp1_lse_enable()
1352 		mmio_clrsetbits_32(rcc_base + RCC_BDCR,  in stm32mp1_lse_enable()
1378 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_hse_enable()  local
1381 		mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);  in stm32mp1_hse_enable()
1385 		mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);  in stm32mp1_hse_enable()
1394 		mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);  in stm32mp1_hse_enable()
1398 	if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) &&  in stm32mp1_hse_enable()
1424 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_set_hsidiv()  local
1425 	uintptr_t address = rcc_base + RCC_OCRDYR;  in stm32mp1_set_hsidiv()
1427 	mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,  in stm32mp1_set_hsidiv()
1473 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_check_pll_conf()  local
1474 	uintptr_t pllxcr = rcc_base + pll->pllxcr;  in stm32mp1_check_pll_conf()
1476 	uintptr_t clksrc_address = rcc_base + (clksrc >> 4);  in stm32mp1_check_pll_conf()
1494 	src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;  in stm32mp1_check_pll_conf()
1514 	if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {  in stm32mp1_check_pll_conf()
1525 	if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {  in stm32mp1_check_pll_conf()
1536 	if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {  in stm32mp1_check_pll_conf()
1606 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_pll_config_output()  local
1615 	mmio_write_32(rcc_base + pll->pllxcfgr2, value);  in stm32mp1_pll_config_output()
1622 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_pll_config()  local
1628 	src = mmio_read_32(rcc_base + pll->rckxselr) &  in stm32mp1_pll_config()
1649 	mmio_write_32(rcc_base + pll->pllxcfgr1, value);  in stm32mp1_pll_config()
1653 	mmio_write_32(rcc_base + pll->pllxfracr, value);  in stm32mp1_pll_config()
1656 	mmio_write_32(rcc_base + pll->pllxfracr, value);  in stm32mp1_pll_config()
1659 	mmio_write_32(rcc_base + pll->pllxfracr, value);  in stm32mp1_pll_config()
1813 	uintptr_t rcc_base = stm32mp_rcc_base();  in stm32mp1_clk_init()  local
1919 	if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &  in stm32mp1_clk_init()
1969 	mmio_write_32(rcc_base + RCC_MPCKDIVR,  in stm32mp1_clk_init()
1971 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);  in stm32mp1_clk_init()
1975 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);  in stm32mp1_clk_init()
1979 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);  in stm32mp1_clk_init()
1983 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);  in stm32mp1_clk_init()
1987 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);  in stm32mp1_clk_init()
1991 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);  in stm32mp1_clk_init()
1995 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);  in stm32mp1_clk_init()
2001 	mmio_write_32(rcc_base + RCC_RTCDIVR,  in stm32mp1_clk_init()
2091 			usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR);  in stm32mp1_clk_init()
2123 			usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) &  in stm32mp1_clk_init()
2142 	mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,  in stm32mp1_clk_init()
2179 	uintptr_t rcc_base = stm32mp_rcc_base();  in get_parent_id_parent()  local
2226 		p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &  in get_parent_id_parent()
2235 		p_sel = mmio_read_32(rcc_base + pll->rckxselr) &  in get_parent_id_parent()