955 static void clk_oscillator_check_bypass(struct stm32_clk_priv *priv, int idx,  in clk_oscillator_check_bypass()  argument
958 	struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, idx);  in clk_oscillator_check_bypass()
966 	address = priv->base + bypass_data->offset;  in clk_oscillator_check_bypass()
974 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv)  in stm32_enable_oscillator_hse()  argument
976 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_enable_oscillator_hse()
982 	if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) {  in stm32_enable_oscillator_hse()
986 	clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass);  in stm32_enable_oscillator_hse()
988 	_clk_stm32_enable(priv, _CK_HSE);  in stm32_enable_oscillator_hse()
991 	clk_oscillator_check_bypass(priv, _CK_HSE, digbyp, bypass);  in stm32_enable_oscillator_hse()
994 	clk_oscillator_set_css(priv, _CK_HSE, css);  in stm32_enable_oscillator_hse()
997 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv)  in stm32_enable_oscillator_lse()  argument
999 	struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE);  in stm32_enable_oscillator_lse()
1000 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_enable_oscillator_lse()
1006 	if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) {  in stm32_enable_oscillator_lse()
1010 	clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass);  in stm32_enable_oscillator_lse()
1012 	clk_oscillator_set_drive(priv, _CK_LSE, drive);  in stm32_enable_oscillator_lse()
1014 	_clk_stm32_gate_enable(priv, osc_data->gate_id);  in stm32_enable_oscillator_lse()
1064 static int stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv *priv)  in stm32_clk_oscillators_lse_set_css()  argument
1066 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_clk_oscillators_lse_set_css()
1069 	clk_oscillator_set_css(priv, _CK_LSE, osci->css);  in stm32_clk_oscillators_lse_set_css()
1077 	struct stm32_clk_priv *priv = clk_stm32_get_priv();  in stm32mp1_come_back_to_hsi()  local
1080 	ret = _clk_stm32_set_parent(priv, _CKMPU, _CK_HSI);  in stm32mp1_come_back_to_hsi()
1085 	ret = _clk_stm32_set_parent(priv, _CKAXI, _CK_HSI);  in stm32mp1_come_back_to_hsi()
1090 	ret = _clk_stm32_set_parent(priv, _CKMLAHB, _CK_HSI);  in stm32mp1_come_back_to_hsi()
1098 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data)  in stm32_clk_configure_clk_get_binding_id()  argument
1102 	return clk_get_index(priv, binding_id);  in stm32_clk_configure_clk_get_binding_id()
1105 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)  in stm32_clk_configure_clk()  argument
1112 	clk_id = stm32_clk_configure_clk_get_binding_id(priv, data);  in stm32_clk_configure_clk()
1117 	ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel);  in stm32_clk_configure_clk()
1123 		clk_stm32_enable_call_ops(priv, clk_id);  in stm32_clk_configure_clk()
1125 		clk_stm32_disable_call_ops(priv, clk_id);  in stm32_clk_configure_clk()
1131 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data)  in stm32_clk_configure_mux()  argument
1136 	return clk_mux_set_parent(priv, mux, sel);  in stm32_clk_configure_mux()
1139 static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv)  in stm32_clk_dividers_configure()  argument
1141 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_clk_dividers_configure()
1153 		ret = clk_stm32_set_div(priv, div_id, div_n);  in stm32_clk_dividers_configure()
1162 static int stm32_clk_source_configure(struct stm32_clk_priv *priv)  in stm32_clk_source_configure()  argument
1164 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_clk_source_configure()
1188 			ret = stm32_clk_configure_mux(priv, cmd_data);  in stm32_clk_source_configure()
1192 			clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data);  in stm32_clk_source_configure()
1195 				if ((_clk_stm32_is_enabled(priv, _RTCCK) == true)) {  in stm32_clk_source_configure()
1200 			ret = stm32_clk_configure_clk(priv, cmd_data);  in stm32_clk_source_configure()
1219 		ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED);  in stm32_clk_source_configure()
1228 static int stm32_clk_stgen_configure(struct stm32_clk_priv *priv, int id)  in stm32_clk_stgen_configure()  argument
1232 	stgen_freq = _clk_stm32_get_rate(priv, id);  in stm32_clk_stgen_configure()
1246 static int clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv *priv,  in clk_stm32_pll_compute_cfgr1()  argument
1256 	prate = _clk_stm32_get_parent_rate(priv, pll->clk_id);  in clk_stm32_pll_compute_cfgr1()
1287 static void clk_stm32_pll_config_vco(struct stm32_clk_priv *priv,  in clk_stm32_pll_config_vco()  argument
1291 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_vco()
1294 	if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) {  in clk_stm32_pll_config_vco()
1310 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv,  in clk_stm32_pll_config_csg()  argument
1314 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_csg()
1336 static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll,  in clk_stm32_pll_config_out()  argument
1339 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_out()
1349 	struct stm32_clk_priv *priv = clk_stm32_get_priv();  in clk_stm32_pll_get_pdata()  local
1350 	struct stm32_clk_platdata *pdata = priv->pdata;  in clk_stm32_pll_get_pdata()
1355 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_is_enabled()  argument
1357 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_is_enabled()
1362 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_set_on()  argument
1364 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_set_on()
1371 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_set_off()  argument
1373 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_set_off()
1382 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv,  in _clk_stm32_pll_wait_ready_on()  argument
1385 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_wait_ready_on()
1400 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv,  in _clk_stm32_pll_wait_ready_off()  argument
1403 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_wait_ready_off()
1418 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_enable()  argument
1420 	if (_clk_stm32_pll_is_enabled(priv, pll)) {  in _clk_stm32_pll_enable()
1425 	_clk_stm32_pll_set_on(priv, pll);  in _clk_stm32_pll_enable()
1428 	return _clk_stm32_pll_wait_ready_on(priv, pll);  in _clk_stm32_pll_enable()
1431 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_disable()  argument
1433 	if (!_clk_stm32_pll_is_enabled(priv, pll)) {  in _clk_stm32_pll_disable()
1438 	_clk_stm32_pll_set_off(priv, pll);  in _clk_stm32_pll_disable()
1441 	_clk_stm32_pll_wait_ready_off(priv, pll);  in _clk_stm32_pll_disable()
1444 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx,  in _clk_stm32_pll_init()  argument
1448 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_init()
1452 	ret = stm32_clk_configure_mux(priv, pll_conf->vco.src);  in _clk_stm32_pll_init()
1459 		clk_stm32_pll_config_out(priv, pll, &pll_conf->output);  in _clk_stm32_pll_init()
1468 	_clk_stm32_pll_disable(priv, pll);  in _clk_stm32_pll_init()
1470 	clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);  in _clk_stm32_pll_init()
1471 	clk_stm32_pll_config_out(priv, pll, &pll_conf->output);  in _clk_stm32_pll_init()
1472 	clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco);  in _clk_stm32_pll_init()
1474 	ret = _clk_stm32_pll_enable(priv, pll);  in _clk_stm32_pll_init()
1484 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx)  in clk_stm32_pll_init()  argument
1489 		return _clk_stm32_pll_init(priv, pll_idx, pll_conf);  in clk_stm32_pll_init()
1495 static int stm32_clk_pll_configure(struct stm32_clk_priv *priv)  in stm32_clk_pll_configure()  argument
1499 	err = clk_stm32_pll_init(priv, _PLL1);  in stm32_clk_pll_configure()
1504 	err = clk_stm32_pll_init(priv, _PLL2);  in stm32_clk_pll_configure()
1509 	err = clk_stm32_pll_init(priv, _PLL3);  in stm32_clk_pll_configure()
1514 	err = clk_stm32_pll_init(priv, _PLL4);  in stm32_clk_pll_configure()
1522 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv)  in stm32_clk_oscillators_wait_lse_ready()  argument
1526 	if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) {  in stm32_clk_oscillators_wait_lse_ready()
1527 		ret = clk_oscillator_wait_ready_on(priv, _CK_LSE);  in stm32_clk_oscillators_wait_lse_ready()
1533 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv)  in stm32_clk_oscillators_enable()  argument
1535 	stm32_enable_oscillator_hse(priv);  in stm32_clk_oscillators_enable()
1536 	stm32_enable_oscillator_lse(priv);  in stm32_clk_oscillators_enable()
1537 	_clk_stm32_enable(priv, _CK_LSI);  in stm32_clk_oscillators_enable()
1538 	_clk_stm32_enable(priv, _CK_CSI);  in stm32_clk_oscillators_enable()
1541 static int stm32_clk_hsidiv_configure(struct stm32_clk_priv *priv)  in stm32_clk_hsidiv_configure()  argument
1543 	return stm32mp1_hsidiv(_clk_stm32_get_rate(priv, _CK_HSI));  in stm32_clk_hsidiv_configure()
1547 static bool stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv *priv, int usbphy_p)  in stm32mp1_clk_is_pll4_used_by_bootrom()  argument
1559 static int stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv *priv, int usbphy_p, int usbo_p)  in stm32mp1_clk_check_usb_conflict()  argument
1568 	_usbo_p = _clk_stm32_get_parent(priv, _USBO_K);  in stm32mp1_clk_check_usb_conflict()
1569 	_usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K);  in stm32mp1_clk_check_usb_conflict()
1635 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv,  int id,  in clk_stm32_pll_recalc_rate()  argument
1638 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_stm32_pll_recalc_rate()
1641 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_recalc_rate()
1673 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id)  in clk_stm32_pll_is_enabled()  argument
1675 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_stm32_pll_is_enabled()
1679 	return _clk_stm32_pll_is_enabled(priv, pll);  in clk_stm32_pll_is_enabled()
1682 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id)  in clk_stm32_pll_enable()  argument
1684 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_stm32_pll_enable()
1688 	return _clk_stm32_pll_enable(priv, pll);  in clk_stm32_pll_enable()
1691 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id)  in clk_stm32_pll_disable()  argument
1693 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_stm32_pll_disable()
1697 	_clk_stm32_pll_disable(priv, pll);  in clk_stm32_pll_disable()
1722 static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv,  in clk_stm32_composite_recalc_rate()  argument
1725 	const struct clk_stm32 *clk = _clk_get(priv, idx);  in clk_stm32_composite_recalc_rate()
1728 	return _clk_stm32_divider_recalc(priv, composite_cfg->div_id, prate);  in clk_stm32_composite_recalc_rate()
1731 static bool clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv *priv, int idx)  in clk_stm32_composite_gate_is_enabled()  argument
1733 	const struct clk_stm32 *clk = _clk_get(priv, idx);  in clk_stm32_composite_gate_is_enabled()
1736 	return _clk_stm32_gate_is_enabled(priv, composite_cfg->gate_id);  in clk_stm32_composite_gate_is_enabled()
1739 static int clk_stm32_composite_gate_enable(struct stm32_clk_priv *priv, int idx)  in clk_stm32_composite_gate_enable()  argument
1741 	const struct clk_stm32 *clk = _clk_get(priv, idx);  in clk_stm32_composite_gate_enable()
1744 	return _clk_stm32_gate_enable(priv, composite_cfg->gate_id);  in clk_stm32_composite_gate_enable()
1747 static void clk_stm32_composite_gate_disable(struct stm32_clk_priv *priv, int idx)  in clk_stm32_composite_gate_disable()  argument
1749 	const struct clk_stm32 *clk = _clk_get(priv, idx);  in clk_stm32_composite_gate_disable()
1752 	_clk_stm32_gate_disable(priv, composite_cfg->gate_id);  in clk_stm32_composite_gate_disable()
1993 	struct stm32_clk_priv *priv = clk_stm32_get_priv();  in stm32mp1_init_clock_tree()  local
1997 	int usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K);  in stm32mp1_init_clock_tree()
1998 	int usbo_p = _clk_stm32_get_parent(priv, _USBO_K);  in stm32mp1_init_clock_tree()
2001 	pll4_bootrom = stm32mp1_clk_is_pll4_used_by_bootrom(priv, usbphy_p);  in stm32mp1_init_clock_tree()
2008 	stm32_clk_oscillators_enable(priv);  in stm32mp1_init_clock_tree()
2016 	ret = stm32_clk_hsidiv_configure(priv);  in stm32mp1_init_clock_tree()
2021 	ret = stm32_clk_stgen_configure(priv, _STGENC);  in stm32mp1_init_clock_tree()
2026 	ret = stm32_clk_dividers_configure(priv);  in stm32mp1_init_clock_tree()
2031 	ret = stm32_clk_pll_configure(priv);  in stm32mp1_init_clock_tree()
2037 	ret = stm32_clk_oscillators_wait_lse_ready(priv);  in stm32mp1_init_clock_tree()
2043 	ret = stm32_clk_source_configure(priv);  in stm32mp1_init_clock_tree()
2049 	ret = stm32_clk_oscillators_lse_set_css(priv);  in stm32mp1_init_clock_tree()
2055 	ret = stm32mp1_clk_check_usb_conflict(priv, usbphy_p, usbo_p);  in stm32mp1_init_clock_tree()
2061 	ret = stm32_clk_stgen_configure(priv, _STGENC);  in stm32mp1_init_clock_tree()
2067 	mmio_clrsetbits_32(priv->base + RCC_DDRITFCR,  in stm32mp1_init_clock_tree()