Lines Matching refs:STM32_GATE
1830 STM32_GATE(_DDRC1, DDRC1, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1),
1831 STM32_GATE(_DDRC1LP, DDRC1LP, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1LP),
1832 STM32_GATE(_DDRPHYC, DDRPHYC, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYC),
1833 STM32_GATE(_DDRPHYCLP, DDRPHYCLP, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYCLP),
1834 STM32_GATE(_DDRCAPB, DDRCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPB),
1835 STM32_GATE(_DDRCAPBLP, DDRCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPBLP),
1836 STM32_GATE(_AXIDCG, AXIDCG, _CKAXI, CLK_IS_CRITICAL, GATE_AXIDCG),
1837 STM32_GATE(_DDRPHYCAPB, DDRPHYCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPB),
1838 STM32_GATE(_DDRPHYCAPBLP, DDRPHYCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPBLP),
1840 STM32_GATE(_SYSCFG, SYSCFG, _PCLK3, 0, GATE_SYSCFG),
1841 STM32_GATE(_DDRPERFM, DDRPERFM, _PCLK4, 0, GATE_DDRPERFM),
1842 STM32_GATE(_IWDG2APB, IWDG2, _PCLK4, 0, GATE_IWDG2APB),
1843 STM32_GATE(_USBPHY_K, USBPHY_K, MUX(MUX_USBPHY), 0, GATE_USBPHY),
1844 STM32_GATE(_USBO_K, USBO_K, MUX(MUX_USBO), 0, GATE_USBO),
1846 STM32_GATE(_RTCAPB, RTCAPB, _PCLK5, CLK_IS_CRITICAL, GATE_RTCAPB),
1847 STM32_GATE(_TZC, TZC, _PCLK5, CLK_IS_CRITICAL, GATE_TZC),
1848 STM32_GATE(_ETZPC, TZPC, _PCLK5, CLK_IS_CRITICAL, GATE_ETZPC),
1849 STM32_GATE(_IWDG1APB, IWDG1, _PCLK5, 0, GATE_IWDG1APB),
1850 STM32_GATE(_BSEC, BSEC, _PCLK5, CLK_IS_CRITICAL, GATE_BSEC),
1851 STM32_GATE(_STGENC, STGEN_K, MUX(MUX_STGEN), CLK_IS_CRITICAL, GATE_STGENC),
1853 STM32_GATE(_USART1_K, USART1_K, MUX(MUX_UART1), 0, GATE_USART1),
1854 STM32_GATE(_USART2_K, USART2_K, MUX(MUX_UART2), 0, GATE_USART2),
1855 STM32_GATE(_I2C3_K, I2C3_K, MUX(MUX_I2C3), 0, GATE_I2C3),
1856 STM32_GATE(_I2C4_K, I2C4_K, MUX(MUX_I2C4), 0, GATE_I2C4),
1857 STM32_GATE(_I2C5_K, I2C5_K, MUX(MUX_I2C5), 0, GATE_I2C5),
1858 STM32_GATE(_TIM12, TIM12_K, _CKTIMG3, 0, GATE_TIM12),
1859 STM32_GATE(_TIM15, TIM15_K, _CKTIMG3, 0, GATE_TIM15),
1861 STM32_GATE(_RTCCK, RTC, MUX(MUX_RTC), 0, GATE_RTCCK),
1863 STM32_GATE(_GPIOA, GPIOA, _CKMLAHB, 0, GATE_GPIOA),
1864 STM32_GATE(_GPIOB, GPIOB, _CKMLAHB, 0, GATE_GPIOB),
1865 STM32_GATE(_GPIOC, GPIOC, _CKMLAHB, 0, GATE_GPIOC),
1866 STM32_GATE(_GPIOD, GPIOD, _CKMLAHB, 0, GATE_GPIOD),
1867 STM32_GATE(_GPIOE, GPIOE, _CKMLAHB, 0, GATE_GPIOE),
1868 STM32_GATE(_GPIOF, GPIOF, _CKMLAHB, 0, GATE_GPIOF),
1869 STM32_GATE(_GPIOG, GPIOG, _CKMLAHB, 0, GATE_GPIOG),
1870 STM32_GATE(_GPIOH, GPIOH, _CKMLAHB, 0, GATE_GPIOH),
1871 STM32_GATE(_GPIOI, GPIOI, _CKMLAHB, 0, GATE_GPIOI),
1873 STM32_GATE(_PKA, PKA, _CKAXI, 0, GATE_PKA),
1874 STM32_GATE(_SAES_K, SAES_K, MUX(MUX_SAES), 0, GATE_SAES),
1875 STM32_GATE(_CRYP1, CRYP1, _PCLK5, 0, GATE_CRYP1),
1876 STM32_GATE(_HASH1, HASH1, _PCLK5, 0, GATE_HASH1),
1878 STM32_GATE(_RNG1_K, RNG1_K, MUX(MUX_RNG1), 0, GATE_RNG1),
1879 STM32_GATE(_BKPSRAM, BKPSRAM, _PCLK5, CLK_IS_CRITICAL, GATE_BKPSRAM),
1881 STM32_GATE(_SDMMC1_K, SDMMC1_K, MUX(MUX_SDMMC1), 0, GATE_SDMMC1),
1882 STM32_GATE(_SDMMC2_K, SDMMC2_K, MUX(MUX_SDMMC2), 0, GATE_SDMMC2),
1883 STM32_GATE(_DBGCK, CK_DBG, _CKAXI, 0, GATE_DBGCK),
1886 STM32_GATE(_USART3_K, USART3_K, MUX(MUX_UART35), 0, GATE_USART3),
1887 STM32_GATE(_UART4_K, UART4_K, MUX(MUX_UART4), 0, GATE_UART4),
1888 STM32_GATE(_UART5_K, UART5_K, MUX(MUX_UART35), 0, GATE_UART5),
1889 STM32_GATE(_UART7_K, UART7_K, MUX(MUX_UART78), 0, GATE_UART7),
1890 STM32_GATE(_UART8_K, UART8_K, MUX(MUX_UART78), 0, GATE_UART8),
1891 STM32_GATE(_USART6_K, USART6_K, MUX(MUX_UART6), 0, GATE_USART6),
1892 STM32_GATE(_MCE, MCE, _CKAXI, CLK_IS_CRITICAL, GATE_MCE),
1893 STM32_GATE(_FMC_K, FMC_K, MUX(MUX_FMC), 0, GATE_FMC),
1894 STM32_GATE(_QSPI_K, QSPI_K, MUX(MUX_QSPI), 0, GATE_QSPI),
1901 STM32_GATE(_TIM2, TIM2_K, _CKTIMG1, 0, GATE_TIM2),
1902 STM32_GATE(_TIM3, TIM3_K, _CKTIMG1, 0, GATE_TIM3),
1903 STM32_GATE(_TIM4, TIM4_K, _CKTIMG1, 0, GATE_TIM4),
1904 STM32_GATE(_TIM5, TIM5_K, _CKTIMG1, 0, GATE_TIM5),
1905 STM32_GATE(_TIM6, TIM6_K, _CKTIMG1, 0, GATE_TIM6),
1906 STM32_GATE(_TIM7, TIM7_K, _CKTIMG1, 0, GATE_TIM7),
1907 STM32_GATE(_TIM13, TIM13_K, _CKTIMG3, 0, GATE_TIM13),
1908 STM32_GATE(_TIM14, TIM14_K, _CKTIMG3, 0, GATE_TIM14),
1909 STM32_GATE(_LPTIM1_K, LPTIM1_K, MUX(MUX_LPTIM1), 0, GATE_LPTIM1),
1910 STM32_GATE(_SPI2_K, SPI2_K, MUX(MUX_SPI23), 0, GATE_SPI2),
1911 STM32_GATE(_SPI3_K, SPI3_K, MUX(MUX_SPI23), 0, GATE_SPI3),
1912 STM32_GATE(_SPDIF_K, SPDIF_K, MUX(MUX_SPDIF), 0, GATE_SPDIF),
1913 STM32_GATE(_TIM1, TIM1_K, _CKTIMG2, 0, GATE_TIM1),
1914 STM32_GATE(_TIM8, TIM8_K, _CKTIMG2, 0, GATE_TIM8),
1915 STM32_GATE(_TIM16, TIM16_K, _CKTIMG3, 0, GATE_TIM16),
1916 STM32_GATE(_TIM17, TIM17_K, _CKTIMG3, 0, GATE_TIM17),
1917 STM32_GATE(_SPI1_K, SPI1_K, MUX(MUX_SPI1), 0, GATE_SPI1),
1918 STM32_GATE(_SPI4_K, SPI4_K, MUX(MUX_SPI4), 0, GATE_SPI4),
1919 STM32_GATE(_SPI5_K, SPI5_K, MUX(MUX_SPI5), 0, GATE_SPI5),
1920 STM32_GATE(_SAI1_K, SAI1_K, MUX(MUX_SAI1), 0, GATE_SAI1),
1921 STM32_GATE(_SAI2_K, SAI2_K, MUX(MUX_SAI2), 0, GATE_SAI2),
1922 STM32_GATE(_DFSDM, DFSDM_K, MUX(MUX_SAI1), 0, GATE_DFSDM),
1923 STM32_GATE(_FDCAN_K, FDCAN_K, MUX(MUX_FDCAN), 0, GATE_FDCAN),
1924 STM32_GATE(_USBH, USBH, _CKAXI, 0, GATE_USBH),
1925 STM32_GATE(_I2C1_K, I2C1_K, MUX(MUX_I2C12), 0, GATE_I2C1),
1926 STM32_GATE(_I2C2_K, I2C2_K, MUX(MUX_I2C12), 0, GATE_I2C2),
1927 STM32_GATE(_ADFSDM, ADFSDM_K, MUX(MUX_SAI1), 0, GATE_ADFSDM),
1928 STM32_GATE(_LPTIM2_K, LPTIM2_K, MUX(MUX_LPTIM2), 0, GATE_LPTIM2),
1929 STM32_GATE(_LPTIM3_K, LPTIM3_K, MUX(MUX_LPTIM3), 0, GATE_LPTIM3),
1930 STM32_GATE(_LPTIM4_K, LPTIM4_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM4),
1931 STM32_GATE(_LPTIM5_K, LPTIM5_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM5),
1932 STM32_GATE(_VREF, VREF, _PCLK3, 0, GATE_VREF),
1933 STM32_GATE(_DTS, TMPSENS, _PCLK3, 0, GATE_DTS),
1934 STM32_GATE(_PMBCTRL, PMBCTRL, _PCLK3, 0, GATE_HDP),
1935 STM32_GATE(_HDP, HDP, _PCLK3, 0, GATE_PMBCTRL),
1936 STM32_GATE(_STGENRO, STGENRO, _PCLK4, 0, GATE_DCMIPP),
1937 STM32_GATE(_DCMIPP_K, DCMIPP_K, MUX(MUX_DCMIPP), 0, GATE_DCMIPP),
1938 STM32_GATE(_DMAMUX1, DMAMUX1, _CKAXI, 0, GATE_DMAMUX1),
1939 STM32_GATE(_DMAMUX2, DMAMUX2, _CKAXI, 0, GATE_DMAMUX2),
1940 STM32_GATE(_DMA3, DMA3, _CKAXI, 0, GATE_DMAMUX2),
1941 STM32_GATE(_ADC1_K, ADC1_K, MUX(MUX_ADC1), 0, GATE_ADC1),
1942 STM32_GATE(_ADC2_K, ADC2_K, MUX(MUX_ADC2), 0, GATE_ADC2),
1943 STM32_GATE(_TSC, TSC, _CKAXI, 0, GATE_TSC),
1944 STM32_GATE(_AXIMC, AXIMC, _CKAXI, 0, GATE_AXIMC),
1945 STM32_GATE(_CRC1, CRC1, _CKAXI, 0, GATE_ETH1TX),
1946 STM32_GATE(_ETH1CK, ETH1CK_K, MUX(MUX_ETH1), 0, GATE_ETH1CK),
1947 STM32_GATE(_ETH1TX, ETH1TX, _CKAXI, 0, GATE_ETH1TX),
1948 STM32_GATE(_ETH1RX, ETH1RX, _CKAXI, 0, GATE_ETH1RX),
1949 STM32_GATE(_ETH2CK, ETH2CK_K, MUX(MUX_ETH2), 0, GATE_ETH2CK),
1950 STM32_GATE(_ETH2TX, ETH2TX, _CKAXI, 0, GATE_ETH2TX),
1951 STM32_GATE(_ETH2RX, ETH2RX, _CKAXI, 0, GATE_ETH2RX),
1952 STM32_GATE(_ETH2MAC, ETH2MAC, _CKAXI, 0, GATE_ETH2MAC),