42 static uint32_t fspi_readl(uint32_t x_addr)  in fspi_readl()  function
51 	ui_reg = fspi_readl(FSPI_MCR0);  in fspi_MDIS()
64 	VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));  in fspi_lock_LUT()
66 	VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));  in fspi_lock_LUT()
72 	VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));  in fspi_unlock_LUT()
74 	VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));  in fspi_unlock_LUT()
198 	reg = fspi_readl(FSPI_MCR0);  in fspi_ahb_invalidate()
201 	while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST) != 0)  in fspi_ahb_invalidate()
225 	INFO("xAhbcr=0x%x\n", fspi_readl(FSPI_AHBCR));  in fspi_init_ahb()
228 	x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2);  in fspi_init_ahb()
238 	x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2);  in fspi_init_ahb()
299 	PRA("0x%x", fspi_readl(FSPI_INTR));  in xspi_ip_read()
313 		PRA("0x%x", fspi_readl(FSPI_IPCR0));  in xspi_ip_read()
323 		PRA("0x%x", fspi_readl(FSPI_IPCR1));  in xspi_ip_read()
326 			sts0 = fspi_readl(FSPI_STS0);  in xspi_ip_read()
332 		PRA("0x%x", fspi_readl(FSPI_IPCMD));  in xspi_ip_read()
334 		intr = fspi_readl(FSPI_INTR);  in xspi_ip_read()
343 			if ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK) == 0) {  in xspi_ip_read()
344 				PRA("0x%x", fspi_readl(FSPI_INTR));  in xspi_ip_read()
347 			while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK)) {  in xspi_ip_read()
348 				PRA("0x%x", fspi_readl(FSPI_INTR));  in xspi_ip_read()
354 				data = fspi_readl(FSPI_RFDR + j);  in xspi_ip_read()
370 			while (!(fspi_readl(FSPI_IPRXFSTS) & FSPI_IPRXFSTS_FILL_MASK)) {  in xspi_ip_read()
371 				PRA("0x%x", fspi_readl(FSPI_IPRXFSTS));  in xspi_ip_read()
378 				data =  fspi_readl(FSPI_RFDR + j);  in xspi_ip_read()
389 		while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK)) {  in xspi_ip_read()
390 			PRA("0x%x", fspi_readl(FSPI_INTR));  in xspi_ip_read()
441 			while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE_MASK) == 0)  in xspi_ip_write()
462 			while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE))  in xspi_ip_write()
487 		while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK))  in xspi_ip_write()
590 	while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0)  in xspi_wren()
604 	while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0)  in fspi_bbluk_er()
615 	iprxfcr = fspi_readl(FSPI_IPRXFCR);  in fspi_RDSR()
629 	while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0)  in fspi_RDSR()
633 	data = fspi_readl(FSPI_RFDR);  in fspi_RDSR()
681 	while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) {  in fspi_sec_er()
682 		PRA("0x%x", fspi_readl(FSPI_INTR));  in fspi_sec_er()
737 	VERBOSE("Flexspi: Register FSPI_MCR0(0x%x) = 0x%08x\n", FSPI_MCR0, fspi_readl(FSPI_MCR0));  in fspi_dump_regs()
738 	VERBOSE("Flexspi: Register FSPI_MCR2(0x%x) = 0x%08x\n", FSPI_MCR2, fspi_readl(FSPI_MCR2));  in fspi_dump_regs()
739 	VERBOSE("Flexspi: Register FSPI_DLL_A_CR(0x%x) = 0x%08x\n", FSPI_DLLACR, fspi_readl(FSPI_DLLACR));  in fspi_dump_regs()
743 …ster FSPI_AHBRX_BUF0CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF0CR0 + i * 4, fspi_readl((FSPI_AHBRX_BUF0…  in fspi_dump_regs()
747 …VERBOSE("Flexspi: Register FSPI_AHBRX_BUF7CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF7CR0, fspi_readl(FS…  in fspi_dump_regs()
748 	VERBOSE("Flexspi: Register FSPI_AHB_CR(0x%x) \t  = 0x%08x\n", FSPI_AHBCR, fspi_readl(FSPI_AHBCR));  in fspi_dump_regs()
752 … Register FSPI_FLSH_A1_CR2,(0x%x) = 0x%08x\n", FSPI_FLSHA1CR2 + i * 4, fspi_readl(FSPI_FLSHA1CR2 +…  in fspi_dump_regs()
771 	INFO("Flexspi: Default MCR0 = 0x%08x, before reset\n", fspi_readl(FSPI_MCR0));  in fspi_init()
776 	while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST))  in fspi_init()
787 	mcrx = fspi_readl(FSPI_MCR0);  in fspi_init()
820 	INFO("Flexspi: After MCR0 = 0x%08x,\n", fspi_readl(FSPI_MCR0));  in fspi_init()