2488 	struct ddr_cfg_regs *regs = &priv->ddr_reg;  in compute_ddr_phy()  local
2532 	input.mr[0] = regs->sdram_mode[0] & U(0xffff);  in compute_ddr_phy()
2533 	input.mr[1] = regs->sdram_mode[0] >> 16U;  in compute_ddr_phy()
2534 	input.mr[2] = regs->sdram_mode[1] >> 16U;  in compute_ddr_phy()
2535 	input.mr[3] = regs->sdram_mode[1] & U(0xffff);  in compute_ddr_phy()
2536 	input.mr[4] = regs->sdram_mode[8] >> 16U;  in compute_ddr_phy()
2537 	input.mr[5] = regs->sdram_mode[8] & U(0xffff);  in compute_ddr_phy()
2538 	input.mr[6] = regs->sdram_mode[9] >> 16U;  in compute_ddr_phy()
2542 		if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0U) {  in compute_ddr_phy()
2545 		odt_rd = (regs->cs[i].config >> 20U) & U(0x7);  in compute_ddr_phy()
2546 		odt_wr = (regs->cs[i].config >> 16U) & U(0x7);  in compute_ddr_phy()
2555 		regs->sdram_cfg[0] &= ~(1 << 28U);  in compute_ddr_phy()
2556 		regs->sdram_cfg[1] &= ~(1 << 2U);  in compute_ddr_phy()
2557 		input.rcw[0] = (regs->sdram_rcw[0] >> 28U) & U(0xf);  in compute_ddr_phy()
2558 		input.rcw[1] = (regs->sdram_rcw[0] >> 24U) & U(0xf);  in compute_ddr_phy()
2559 		input.rcw[2] = (regs->sdram_rcw[0] >> 20U) & U(0xf);  in compute_ddr_phy()
2560 		input.rcw[3] = (regs->sdram_rcw[0] >> 16U) & U(0xf);  in compute_ddr_phy()
2561 		input.rcw[4] = (regs->sdram_rcw[0] >> 12U) & U(0xf);  in compute_ddr_phy()
2562 		input.rcw[5] = (regs->sdram_rcw[0] >> 8U) & U(0xf);  in compute_ddr_phy()
2563 		input.rcw[6] = (regs->sdram_rcw[0] >> 4U) & U(0xf);  in compute_ddr_phy()
2564 		input.rcw[7] = (regs->sdram_rcw[0] >> 0U) & U(0xf);  in compute_ddr_phy()
2565 		input.rcw[8] = (regs->sdram_rcw[1] >> 28U) & U(0xf);  in compute_ddr_phy()
2566 		input.rcw[9] = (regs->sdram_rcw[1] >> 24U) & U(0xf);  in compute_ddr_phy()
2567 		input.rcw[10] = (regs->sdram_rcw[1] >> 20U) & U(0xf);  in compute_ddr_phy()
2568 		input.rcw[11] = (regs->sdram_rcw[1] >> 16U) & U(0xf);  in compute_ddr_phy()
2569 		input.rcw[12] = (regs->sdram_rcw[1] >> 12U) & U(0xf);  in compute_ddr_phy()
2570 		input.rcw[13] = (regs->sdram_rcw[1] >> 8U) & U(0xf);  in compute_ddr_phy()
2571 		input.rcw[14] = (regs->sdram_rcw[1] >> 4U) & U(0xf);  in compute_ddr_phy()
2572 		input.rcw[15] = (regs->sdram_rcw[1] >> 0U) & U(0xf);  in compute_ddr_phy()
2573 		input.rcw3x = (regs->sdram_rcw[2] >> 8U) & U(0xff);  in compute_ddr_phy()
2615 		regs->timing_cfg[0] = ddrctrl_regs.timing_cfg0;  in compute_ddr_phy()
2616 		regs->timing_cfg[4] = ddrctrl_regs.timing_cfg4;  in compute_ddr_phy()
2648 			tcfg0 = regs->timing_cfg[0];  in compute_ddr_phy()
2649 			tcfg4 = regs->timing_cfg[4];  in compute_ddr_phy()
2653 			regs->timing_cfg[0] = tcfg0;  in compute_ddr_phy()
2654 			regs->timing_cfg[4] = tcfg4;  in compute_ddr_phy()
2681 			ddrctrl_regs.timing_cfg0 = regs->timing_cfg[0];  in compute_ddr_phy()
2682 			ddrctrl_regs.timing_cfg4 = regs->timing_cfg[4];  in compute_ddr_phy()