Lines Matching refs:basic
618 if (input->basic.dimm_type != RDIMM) { in prog_acsm_playback()
644 if (input->basic.dimm_type != RDIMM) { in prog_acsm_ctr()
682 frq = input->basic.frequency >> 1; in prog_seq0bdly0()
684 if (input->basic.frequency < 400) { in prog_seq0bdly0()
685 lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 7 : 3; in prog_seq0bdly0()
686 } else if (input->basic.frequency < 533) { in prog_seq0bdly0()
687 lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 14 : 11; in prog_seq0bdly0()
749 load_pieimage(phy, input->basic.dimm_type); in i_load_pie()
765 input->basic.dimm_type == RDIMM && in i_load_pie()
777 input->basic.dimm_type == RDIMM ? U(0x2) : 0U); in i_load_pie()
819 if (input->basic.dimm_type == RDIMM) { in phy_gen2_init_input()
842 switch (input->basic.dimm_type) { in phy_gen2_msg_init()
869 if (input->basic.dimm_type == LRDIMM) { in phy_gen2_msg_init()
895 msg_blk->enabled_dqs = (input->basic.num_active_dbyte_dfi0 + in phy_gen2_msg_init()
896 input->basic.num_active_dbyte_dfi1) * 8; in phy_gen2_msg_init()
897 msg_blk->x16present = input->basic.dram_data_width == 0x10 ? in phy_gen2_msg_init()
923 msg_blk->dramfreq = input->basic.frequency * 2U; in phy_gen2_msg_init()
924 msg_blk->pll_bypass_en = input->basic.pll_bypass; in phy_gen2_msg_init()
925 msg_blk->dfi_freq_ratio = input->basic.dfi_freq_ratio == 0U ? 1U : in phy_gen2_msg_init()
926 input->basic.dfi_freq_ratio == 1U ? 2U : in phy_gen2_msg_init()
950 if (input->basic.dimm_type == RDIMM || in phy_gen2_msg_init()
951 input->basic.dimm_type == LRDIMM) { in phy_gen2_msg_init()
991 if (input->basic.dimm_type == LRDIMM) { in phy_gen2_msg_init()
1001 if (input->basic.train2d != 0) { in phy_gen2_msg_init()
1039 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_tx_pre_drv_mode()
1061 if (input->basic.num_anib == 8) { in prog_atx_pre_drv_mode()
1064 } else if (input->basic.num_anib == 10 || input->basic.num_anib == 12 || in prog_atx_pre_drv_mode()
1065 input->basic.num_anib == 13) { in prog_atx_pre_drv_mode()
1069 ERROR("Invalid number of aNIBs: %d\n", input->basic.num_anib); in prog_atx_pre_drv_mode()
1073 for (anib = 0; anib < input->basic.num_anib; anib++) { in prog_atx_pre_drv_mode()
1093 if (input->basic.dimm_type != RDIMM && in prog_enable_cs_multicast()
1094 input->basic.dimm_type != LRDIMM) { in prog_enable_cs_multicast()
1128 switch (input->basic.dimm_type) { in prog_dfi_rd_data_cs_dest_map()
1201 if (input->basic.frequency / 2 < 235) { in prog_pll_ctrl2()
1203 } else if (input->basic.frequency / 2 < 313) { in prog_pll_ctrl2()
1205 } else if (input->basic.frequency / 2 < 469) { in prog_pll_ctrl2()
1207 } else if (input->basic.frequency / 2 < 625) { in prog_pll_ctrl2()
1209 } else if (input->basic.frequency / 2 < 938) { in prog_pll_ctrl2()
1211 } else if (input->basic.frequency / 2 < 1067) { in prog_pll_ctrl2()
1255 if (input->basic.frequency >= 933) { in prog_ard_ptr_init_val()
1300 } else if (input->basic.frequency <= 933) { in prog_proc_odt_time_ctl()
1302 } else if (input->basic.frequency <= 1200) { in prog_proc_odt_time_ctl()
1391 input->basic.hard_macro_ver); in prog_tx_odt_drv_stren()
1398 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_tx_odt_drv_stren()
1466 input->basic.hard_macro_ver); in prog_tx_impedance_ctrl1()
1468 input->basic.hard_macro_ver); in prog_tx_impedance_ctrl1()
1472 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_tx_impedance_ctrl1()
1564 if (input->basic.hard_macro_ver == 4 && in prog_atx_impedance()
1571 input->basic.hard_macro_ver); in prog_atx_impedance()
1573 input->basic.hard_macro_ver); in prog_atx_impedance()
1576 for (anib = 0; anib < input->basic.num_anib; anib++) { in prog_atx_impedance()
1589 if (input->basic.dfi1exists == 1) { in prog_dfi_mode()
1638 cal_uclk_ticks_per1u_s = input->basic.frequency >> 1; in prog_cal_uclk_info()
1706 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_dq_dqs_rcv_cntrl()
1730 if (input->basic.dram_type == DDR4 && input->adv.mem_alert_en == 1) { in prog_mem_alert_control()
1756 dfi_freq_ratio = input->basic.dfi_freq_ratio; in prog_dfi_freq_ratio()
1786 pllbypass_dat = input->basic.pll_bypass; /* only [0] is used */ in prog_dfi_xlat()
1816 for (byte = 0; byte < input->basic.num_dbyte; byte++) { in prog_dbyte_misc_mode()
1818 if (byte <= input->basic.num_active_dbyte_dfi0 - 1) { in prog_dbyte_misc_mode()
1820 if ((input->basic.dram_data_width != 4) && in prog_dbyte_misc_mode()
1843 x4tg = input->basic.dram_data_width == 4 ? 0xf : 0; in prog_master_x4config()
2218 switch (input->basic.dimm_type) { in load_fw()
2409 printf("\n \"dram_type\": \"%s\",", dram_types_str[input->basic.dram_type]); in print_jason_format()
2410 printf("\n \"dimm_type\": \"%s\",", dimm_types_str[input->basic.dimm_type]); in print_jason_format()
2411 printf("\n \"hard_macro_ver\": \"%d\",", input->basic.hard_macro_ver); in print_jason_format()
2412 printf("\n \"num_dbyte\": \"0x%04x\",", (unsigned int)input->basic.num_dbyte); in print_jason_format()
2413 …printf("\n \"num_active_dbyte_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_active_dbyte… in print_jason_format()
2414 printf("\n \"num_anib\": \"0x%04x\",", (unsigned int)input->basic.num_anib); in print_jason_format()
2415 printf("\n \"num_rank_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_rank_dfi0); in print_jason_format()
2416 printf("\n \"num_pstates\": \"0x%04x\",", (unsigned int)input->basic.num_pstates); in print_jason_format()
2417 printf("\n \"frequency\": \"%d\",", input->basic.frequency); in print_jason_format()
2418 printf("\n \"pll_bypass\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio); in print_jason_format()
2419 printf("\n \"dfi_freq_ratio\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio); in print_jason_format()
2420 printf("\n \"dfi1_exists\": \"0x%04x\",", (unsigned int)input->basic.dfi1exists); in print_jason_format()
2421 printf("\n \"dram_data_width\": \"0x%04x\",", (unsigned int)input->basic.dram_data_width); in print_jason_format()
2512 input.basic.dram_type = DDR4; in compute_ddr_phy()
2514 input.basic.dimm_type = (dimm_param->rdimm != 0) ? RDIMM : UDIMM; in compute_ddr_phy()
2515 input.basic.num_dbyte = dimm_param->primary_sdram_width / 8 + in compute_ddr_phy()
2517 input.basic.num_active_dbyte_dfi0 = input.basic.num_dbyte; in compute_ddr_phy()
2518 input.basic.num_rank_dfi0 = dimm_param->n_ranks; in compute_ddr_phy()
2519 input.basic.dram_data_width = dimm_param->device_width; in compute_ddr_phy()
2520 input.basic.hard_macro_ver = 0xa; in compute_ddr_phy()
2521 input.basic.num_pstates = 1; in compute_ddr_phy()
2522 input.basic.dfi_freq_ratio = 1; in compute_ddr_phy()
2523 input.basic.num_anib = 0xc; in compute_ddr_phy()
2524 input.basic.train2d = popts->skip2d ? 0 : 1; in compute_ddr_phy()
2525 input.basic.frequency = (int) (clk / 2000000ul); in compute_ddr_phy()
2526 debug("frequency = %dMHz\n", input.basic.frequency); in compute_ddr_phy()
2605 input.basic.train2d in compute_ddr_phy()
2651 get_cdd_val(priv->phy, rank, input.basic.frequency, in compute_ddr_phy()
2658 if ((ret == 0) && (input.basic.train2d != 0)) { in compute_ddr_phy()
2689 input.basic.train2d in compute_ddr_phy()
2707 input.basic.dimm_type == RDIMM ? "RDIMM" : in compute_ddr_phy()
2708 input.basic.dimm_type == LRDIMM ? "LRDIMM" : in compute_ddr_phy()