Lines Matching defs:ddr4u1d
14 struct ddr4u1d { struct
15 uint8_t reserved00;
16 uint8_t msg_misc;
17 uint16_t pmu_revision;
18 uint8_t pstate;
19 uint8_t pll_bypass_en;
20 uint16_t dramfreq;
21 uint8_t dfi_freq_ratio;
22 uint8_t bpznres_val;
23 uint8_t phy_odt_impedance;
24 uint8_t phy_drv_impedance;
25 uint8_t phy_vref;
26 uint8_t dram_type;
27 uint8_t disabled_dbyte;
28 uint8_t enabled_dqs;
29 uint8_t cs_present;
30 uint8_t cs_present_d0;
31 uint8_t cs_present_d1;
32 uint8_t addr_mirror;
33 uint8_t cs_test_fail;
34 uint8_t phy_cfg;
35 uint16_t sequence_ctrl;
36 uint8_t hdt_ctrl;
37 uint8_t reserved19[0x1B - 0x19];
38 uint8_t share2dvref_result;
39 uint8_t reserved1c[0x22 - 0x1c];
40 uint16_t phy_config_override;
41 uint8_t dfimrlmargin;
42 int8_t cdd_rr_3_2;
43 int8_t cdd_rr_3_1;
44 int8_t cdd_rr_3_0;
45 int8_t cdd_rr_2_3;
46 int8_t cdd_rr_2_1;
47 int8_t cdd_rr_2_0;
48 int8_t cdd_rr_1_3;
49 int8_t cdd_rr_1_2;
50 int8_t cdd_rr_1_0;
51 int8_t cdd_rr_0_3;
52 int8_t cdd_rr_0_2;
53 int8_t cdd_rr_0_1;
54 int8_t cdd_ww_3_2;
55 int8_t cdd_ww_3_1;
56 int8_t cdd_ww_3_0;
57 int8_t cdd_ww_2_3;
58 int8_t cdd_ww_2_1;
59 int8_t cdd_ww_2_0;
60 int8_t cdd_ww_1_3;
61 int8_t cdd_ww_1_2;
62 int8_t cdd_ww_1_0;
63 int8_t cdd_ww_0_3;
64 int8_t cdd_ww_0_2;
65 int8_t cdd_ww_0_1;
66 int8_t cdd_rw_3_3;
67 int8_t cdd_rw_3_2;
68 int8_t cdd_rw_3_1;
69 int8_t cdd_rw_3_0;
70 int8_t cdd_rw_2_3;
71 int8_t cdd_rw_2_2;
72 int8_t cdd_rw_2_1;
73 int8_t cdd_rw_2_0;
74 int8_t cdd_rw_1_3;
75 int8_t cdd_rw_1_2;
76 int8_t cdd_rw_1_1;
77 int8_t cdd_rw_1_0;
78 int8_t cdd_rw_0_3;
79 int8_t cdd_rw_0_2;
80 int8_t cdd_rw_0_1;
81 int8_t cdd_rw_0_0;
82 int8_t cdd_wr_3_3;
83 int8_t cdd_wr_3_2;
84 int8_t cdd_wr_3_1;
85 int8_t cdd_wr_3_0;
86 int8_t cdd_wr_2_3;
87 int8_t cdd_wr_2_2;
88 int8_t cdd_wr_2_1;
89 int8_t cdd_wr_2_0;
90 int8_t cdd_wr_1_3;
91 int8_t cdd_wr_1_2;
92 int8_t cdd_wr_1_1;
93 int8_t cdd_wr_1_0;
94 int8_t cdd_wr_0_3;
95 int8_t cdd_wr_0_2;
96 int8_t cdd_wr_0_1;
97 int8_t cdd_wr_0_0;
98 uint8_t reserved5d;
99 uint16_t mr0;
100 uint16_t mr1;
101 uint16_t mr2;
102 uint16_t mr3;
103 uint16_t mr4;
104 uint16_t mr5;
105 uint16_t mr6;
106 uint8_t x16present;
107 uint8_t cs_setup_gddec;
108 uint16_t rtt_nom_wr_park0;
109 uint16_t rtt_nom_wr_park1;
110 uint16_t rtt_nom_wr_park2;
111 uint16_t rtt_nom_wr_park3;
112 uint16_t rtt_nom_wr_park4;
113 uint16_t rtt_nom_wr_park5;
114 uint16_t rtt_nom_wr_park6;
115 uint16_t rtt_nom_wr_park7;
116 uint8_t acsm_odt_ctrl0;
117 uint8_t acsm_odt_ctrl1;
118 uint8_t acsm_odt_ctrl2;
119 uint8_t acsm_odt_ctrl3;
120 uint8_t acsm_odt_ctrl4;
121 uint8_t acsm_odt_ctrl5;
122 uint8_t acsm_odt_ctrl6;
123 uint8_t acsm_odt_ctrl7;
124 uint8_t vref_dq_r0nib0;
125 uint8_t vref_dq_r0nib1;
126 uint8_t vref_dq_r0nib2;
127 uint8_t vref_dq_r0nib3;
128 uint8_t vref_dq_r0nib4;
129 uint8_t vref_dq_r0nib5;
130 uint8_t vref_dq_r0nib6;
131 uint8_t vref_dq_r0nib7;
132 uint8_t vref_dq_r0nib8;
133 uint8_t vref_dq_r0nib9;
134 uint8_t vref_dq_r0nib10;
135 uint8_t vref_dq_r0nib11;
136 uint8_t vref_dq_r0nib12;
137 uint8_t vref_dq_r0nib13;
138 uint8_t vref_dq_r0nib14;
139 uint8_t vref_dq_r0nib15;
140 uint8_t vref_dq_r0nib16;
141 uint8_t vref_dq_r0nib17;
142 uint8_t vref_dq_r0nib18;
143 uint8_t vref_dq_r0nib19;
144 uint8_t vref_dq_r1nib0;
145 uint8_t vref_dq_r1nib1;
146 uint8_t vref_dq_r1nib2;
147 uint8_t vref_dq_r1nib3;
148 uint8_t vref_dq_r1nib4;
149 uint8_t vref_dq_r1nib5;
150 uint8_t vref_dq_r1nib6;
151 uint8_t vref_dq_r1nib7;
152 uint8_t vref_dq_r1nib8;
153 uint8_t vref_dq_r1nib9;
154 uint8_t vref_dq_r1nib10;
155 uint8_t vref_dq_r1nib11;
156 uint8_t vref_dq_r1nib12;
157 uint8_t vref_dq_r1nib13;
158 uint8_t vref_dq_r1nib14;
159 uint8_t vref_dq_r1nib15;
160 uint8_t vref_dq_r1nib16;
161 uint8_t vref_dq_r1nib17;
162 uint8_t vref_dq_r1nib18;
163 uint8_t vref_dq_r1nib19;
164 uint8_t vref_dq_r2nib0;
165 uint8_t vref_dq_r2nib1;
166 uint8_t vref_dq_r2nib2;
167 uint8_t vref_dq_r2nib3;
168 uint8_t vref_dq_r2nib4;
169 uint8_t vref_dq_r2nib5;
170 uint8_t vref_dq_r2nib6;
171 uint8_t vref_dq_r2nib7;
172 uint8_t vref_dq_r2nib8;
173 uint8_t vref_dq_r2nib9;
174 uint8_t vref_dq_r2nib10;
175 uint8_t vref_dq_r2nib11;
176 uint8_t vref_dq_r2nib12;
177 uint8_t vref_dq_r2nib13;
178 uint8_t vref_dq_r2nib14;
179 uint8_t vref_dq_r2nib15;
180 uint8_t vref_dq_r2nib16;
181 uint8_t vref_dq_r2nib17;
182 uint8_t vref_dq_r2nib18;
183 uint8_t vref_dq_r2nib19;
184 uint8_t vref_dq_r3nib0;
185 uint8_t vref_dq_r3nib1;
186 uint8_t vref_dq_r3nib2;
187 uint8_t vref_dq_r3nib3;
188 uint8_t vref_dq_r3nib4;
189 uint8_t vref_dq_r3nib5;
190 uint8_t vref_dq_r3nib6;
191 uint8_t vref_dq_r3nib7;
192 uint8_t vref_dq_r3nib8;
193 uint8_t vref_dq_r3nib9;
194 uint8_t vref_dq_r3nib10;
195 uint8_t vref_dq_r3nib11;
196 uint8_t vref_dq_r3nib12;
197 uint8_t vref_dq_r3nib13;
198 uint8_t vref_dq_r3nib14;
199 uint8_t vref_dq_r3nib15;
200 uint8_t vref_dq_r3nib16;
201 uint8_t vref_dq_r3nib17;
202 uint8_t vref_dq_r3nib18;
203 uint8_t vref_dq_r3nib19;
204 uint8_t reserved_d6[0x3f6 - 0xd6];
205 uint16_t alt_cas_l;
206 uint8_t alt_wcas_l;
207 uint8_t d4misc;