69 	debug("cs%d\n", i);  in cal_csn_config()
70 	debug("   _config = 0x%x\n", regs->cs[i].config);  in cal_csn_config()
236 	debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]);  in cal_timing_cfg()
261 	debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]);  in cal_timing_cfg()
278 	debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]);  in cal_timing_cfg()
288 	debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]);  in cal_timing_cfg()
299 	debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]);  in cal_timing_cfg()
310 	debug("timing_cfg[5] = 0x%x\n", regs->timing_cfg[5]);  in cal_timing_cfg()
317 	debug("timing_cfg[6] = 0x%x\n", regs->timing_cfg[6]);  in cal_timing_cfg()
321 		debug("PAR_LAT = 0x%x\n", par_lat);  in cal_timing_cfg()
329 	debug("timing_cfg[7] = 0x%x\n", regs->timing_cfg[7]);  in cal_timing_cfg()
348 	debug("timing_cfg[8] = 0x%x\n", regs->timing_cfg[8]);  in cal_timing_cfg()
352 	debug("timing_cfg[9] = 0x%x\n", regs->timing_cfg[9]);  in cal_timing_cfg()
399 	debug("sdram_rcw[0] = 0x%x\n", regs->sdram_rcw[0]);  in cal_ddr_sdram_rcw()
400 	debug("sdram_rcw[1] = 0x%x\n", regs->sdram_rcw[1]);  in cal_ddr_sdram_rcw()
401 	debug("sdram_rcw[2] = 0x%x\n", regs->sdram_rcw[2]);  in cal_ddr_sdram_rcw()
468 	debug("sdram_cfg[0] = 0x%x\n", regs->sdram_cfg[0]);  in cal_ddr_sdram_cfg()
493 	debug("sdram_cfg[1] = 0x%x\n", regs->sdram_cfg[1]);  in cal_ddr_sdram_cfg()
505 	debug("sdram_cfg[2] = 0x%x\n", regs->sdram_cfg[2]);  in cal_ddr_sdram_cfg()
519 	debug("interval = 0x%x\n", regs->interval);  in cal_ddr_sdram_interval()
635 	debug("sdram_mode[0] = 0x%x\n", regs->sdram_mode[0]);  in cal_ddr_sdram_mode()
675 	debug("sdram_mode[1] = 0x%x\n", regs->sdram_mode[1]);  in cal_ddr_sdram_mode()
686 	debug("sdram_mode[9] = 0x%x\n", regs->sdram_mode[9]);  in cal_ddr_sdram_mode()
758 			debug("sdram_mode[8] = 0x%x\n", regs->sdram_mode[8]);  in cal_ddr_sdram_mode()
769 			debug("sdram_mode[2] = 0x%x\n", regs->sdram_mode[2]);  in cal_ddr_sdram_mode()
770 			debug("sdram_mode[3] = 0x%x\n", regs->sdram_mode[3]);  in cal_ddr_sdram_mode()
771 			debug("sdram_mode[10] = 0x%x\n", regs->sdram_mode[10]);  in cal_ddr_sdram_mode()
772 			debug("sdram_mode[11] = 0x%x\n", regs->sdram_mode[11]);  in cal_ddr_sdram_mode()
783 			debug("sdram_mode[4] = 0x%x\n", regs->sdram_mode[4]);  in cal_ddr_sdram_mode()
784 			debug("sdram_mode[5] = 0x%x\n", regs->sdram_mode[5]);  in cal_ddr_sdram_mode()
785 			debug("sdram_mode[12] = 0x%x\n", regs->sdram_mode[12]);  in cal_ddr_sdram_mode()
786 			debug("sdram_mode[13] = 0x%x\n", regs->sdram_mode[13]);  in cal_ddr_sdram_mode()
797 			debug("sdram_mode[6] = 0x%x\n", regs->sdram_mode[6]);  in cal_ddr_sdram_mode()
798 			debug("sdram_mode[7] = 0x%x\n", regs->sdram_mode[7]);  in cal_ddr_sdram_mode()
799 			debug("sdram_mode[14] = 0x%x\n", regs->sdram_mode[14]);  in cal_ddr_sdram_mode()
800 			debug("sdram_mode[15] = 0x%x\n", regs->sdram_mode[15]);  in cal_ddr_sdram_mode()
845 	debug("dq_map[0] = 0x%x\n", regs->dq_map[0]);  in cal_ddr_dq_mapping()
846 	debug("dq_map[1] = 0x%x\n", regs->dq_map[1]);  in cal_ddr_dq_mapping()
847 	debug("dq_map[2] = 0x%x\n", regs->dq_map[2]);  in cal_ddr_dq_mapping()
848 	debug("dq_map[3] = 0x%x\n", regs->dq_map[3]);  in cal_ddr_dq_mapping()
863 	debug("zq_cntl = 0x%x\n", regs->zq_cntl);  in cal_ddr_zq_cntl()
873 	debug("ddr_sr_cntr = 0x%x\n", regs->ddr_sr_cntr);  in cal_ddr_sr_cntr()
881 		debug("eor = 0x%x\n", regs->eor);  in cal_ddr_eor()
897 		debug("cs_in_use = 0x%x\n", conf->cs_in_use);  in cal_ddr_csn_bnds()
911 		debug("cs[%d].bnds = 0x%x\n", i, regs->cs[i].bnds);  in cal_ddr_csn_bnds()
965 	debug("col %d, row %d, ba %d, bg %d, intlv %d\n",  in cal_ddr_addr_dec()
983 	debug("cacheline size %d\n", cacheline);  in cal_ddr_addr_dec()
1140 		debug("dec[%d] = 0x%x\n", i, regs->dec[i]);  in cal_ddr_addr_dec()
1317 	debug("Skip CL mask for this speed 0x%x\n", bin[i].cl[k].caslat[j]);  in skip_caslat()
1352 	debug("Skip caslat 0x%x\n", caslat_skip);  in compute_ddrc()