21 static struct spinand_device spinand_dev;  variable
66 	uint8_t cfg = spinand_dev.cfg_cache;  in spi_nand_update_cfg()
71 	if (cfg == spinand_dev.cfg_cache) {  in spi_nand_update_cfg()
77 		spinand_dev.cfg_cache = cfg;  in spi_nand_update_cfg()
93 	if ((spinand_dev.flags & SPI_NAND_HAS_QE_BIT) == 0U) {  in spi_nand_quad_enable()
97 	if (spinand_dev.spi_read_cache_op.data.buswidth ==  in spi_nand_quad_enable()
162 	uint32_t block_nb = page / spinand_dev.nand_dev->block_size;  in spi_nand_load_page()
163 	uint32_t page_nb = page - (block_nb * spinand_dev.nand_dev->page_size);  in spi_nand_load_page()
164 	uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size /  in spi_nand_load_page()
165 				     spinand_dev.nand_dev->page_size;  in spi_nand_load_page()
181 	uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size /  in spi_nand_read_from_cache()
182 				     spinand_dev.nand_dev->page_size;  in spi_nand_read_from_cache()
184 	uint32_t page_sh = __builtin_ctz(spinand_dev.nand_dev->page_size) + 1U;  in spi_nand_read_from_cache()
186 	spinand_dev.spi_read_cache_op.addr.val = offset;  in spi_nand_read_from_cache()
188 	if ((spinand_dev.nand_dev->nb_planes > 1U) && ((block_nb % 2U) == 1U)) {  in spi_nand_read_from_cache()
189 		spinand_dev.spi_read_cache_op.addr.val |= 1U << page_sh;  in spi_nand_read_from_cache()
192 	spinand_dev.spi_read_cache_op.data.buf = buffer;  in spi_nand_read_from_cache()
193 	spinand_dev.spi_read_cache_op.data.nbytes = len;  in spi_nand_read_from_cache()
195 	return spi_mem_exec_op(&spinand_dev.spi_read_cache_op);  in spi_nand_read_from_cache()
234 	unsigned int nbpages_per_block = spinand_dev.nand_dev->block_size /  in spi_nand_mtd_block_is_bad()
235 					 spinand_dev.nand_dev->page_size;  in spi_nand_mtd_block_is_bad()
240 				 spinand_dev.nand_dev->page_size,  in spi_nand_mtd_block_is_bad()
259 				  spinand_dev.nand_dev->page_size, true);  in spi_nand_mtd_read_page()
267 	spinand_dev.nand_dev = get_nand_device();  in spi_nand_init()
268 	if (spinand_dev.nand_dev == NULL) {  in spi_nand_init()
272 	spinand_dev.nand_dev->mtd_block_is_bad = spi_nand_mtd_block_is_bad;  in spi_nand_init()
273 	spinand_dev.nand_dev->mtd_read_page = spi_nand_mtd_read_page;  in spi_nand_init()
274 	spinand_dev.nand_dev->nb_planes = 1;  in spi_nand_init()
276 	spinand_dev.spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE;  in spi_nand_init()
277 	spinand_dev.spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;  in spi_nand_init()
278 	spinand_dev.spi_read_cache_op.addr.nbytes = 2U;  in spi_nand_init()
279 	spinand_dev.spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;  in spi_nand_init()
280 	spinand_dev.spi_read_cache_op.dummy.nbytes = 1U;  in spi_nand_init()
281 	spinand_dev.spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;  in spi_nand_init()
282 	spinand_dev.spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;  in spi_nand_init()
284 	if (plat_get_spi_nand_data(&spinand_dev) != 0) {  in spi_nand_init()
288 	assert((spinand_dev.nand_dev->page_size != 0U) &&  in spi_nand_init()
289 	       (spinand_dev.nand_dev->block_size != 0U) &&  in spi_nand_init()
290 	       (spinand_dev.nand_dev->size != 0U));  in spi_nand_init()
302 	ret = spi_nand_read_reg(SPI_NAND_REG_CFG, &spinand_dev.cfg_cache);  in spi_nand_init()
315 		spinand_dev.nand_dev->page_size,  in spi_nand_init()
316 		spinand_dev.nand_dev->block_size,  in spi_nand_init()
317 		spinand_dev.nand_dev->size);  in spi_nand_init()
319 	*size = spinand_dev.nand_dev->size;  in spi_nand_init()
320 	*erase_size = spinand_dev.nand_dev->block_size;  in spi_nand_init()