Lines Matching refs:data
305 uint32_t mask, data; in mvebu_cp110_comphy_is_pll_locked() local
314 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & in mvebu_cp110_comphy_is_pll_locked()
316 mask = data; in mvebu_cp110_comphy_is_pll_locked()
317 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_is_pll_locked()
319 if (data != 0) { in mvebu_cp110_comphy_is_pll_locked()
320 if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK) in mvebu_cp110_comphy_is_pll_locked()
322 if (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK) in mvebu_cp110_comphy_is_pll_locked()
335 uint32_t mask, data; in mvebu_cp110_polarity_invert() local
338 data = mask = 0x0U; in mvebu_cp110_polarity_invert()
340 data |= (1 << HPIPE_SYNC_PATTERN_TXD_INV_OFFSET); in mvebu_cp110_polarity_invert()
346 data |= (1 << HPIPE_SYNC_PATTERN_RXD_INV_OFFSET); in mvebu_cp110_polarity_invert()
351 reg_set(addr, data, mask); in mvebu_cp110_polarity_invert()
358 uint32_t mask, data; in mvebu_cp110_comphy_sata_power_on() local
386 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in mvebu_cp110_comphy_sata_power_on()
388 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in mvebu_cp110_comphy_sata_power_on()
390 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in mvebu_cp110_comphy_sata_power_on()
392 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in mvebu_cp110_comphy_sata_power_on()
393 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
402 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in mvebu_cp110_comphy_sata_power_on()
404 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
405 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
418 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in mvebu_cp110_comphy_sata_power_on()
421 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
422 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
434 data = sata_static_values->g1_rx_selmupi << in mvebu_cp110_comphy_sata_power_on()
437 data |= sata_static_values->g1_rx_selmupf << in mvebu_cp110_comphy_sata_power_on()
440 data |= sata_static_values->g1_rx_selmufi << in mvebu_cp110_comphy_sata_power_on()
443 data |= sata_static_values->g1_rx_selmuff << in mvebu_cp110_comphy_sata_power_on()
446 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; in mvebu_cp110_comphy_sata_power_on()
447 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
450 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
452 data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
454 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
456 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
458 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
459 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
463 data = sata_static_values->g2_rx_selmupi << in mvebu_cp110_comphy_sata_power_on()
466 data |= sata_static_values->g2_rx_selmupf << in mvebu_cp110_comphy_sata_power_on()
469 data |= sata_static_values->g2_rx_selmufi << in mvebu_cp110_comphy_sata_power_on()
472 data |= sata_static_values->g2_rx_selmuff << in mvebu_cp110_comphy_sata_power_on()
475 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; in mvebu_cp110_comphy_sata_power_on()
476 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
480 data = sata_static_values->g3_rx_selmupi << in mvebu_cp110_comphy_sata_power_on()
483 data |= sata_static_values->g3_rx_selmupf << in mvebu_cp110_comphy_sata_power_on()
486 data |= sata_static_values->g3_rx_selmufi << in mvebu_cp110_comphy_sata_power_on()
489 data |= sata_static_values->g3_rx_selmuff << in mvebu_cp110_comphy_sata_power_on()
492 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; in mvebu_cp110_comphy_sata_power_on()
494 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; in mvebu_cp110_comphy_sata_power_on()
496 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; in mvebu_cp110_comphy_sata_power_on()
497 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
501 data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; in mvebu_cp110_comphy_sata_power_on()
503 data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; in mvebu_cp110_comphy_sata_power_on()
505 data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in mvebu_cp110_comphy_sata_power_on()
507 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
509 data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
511 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
513 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
514 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
518 data = 0x1 << HPIPE_SMAPLER_OFFSET; in mvebu_cp110_comphy_sata_power_on()
519 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
521 data = 0x0 << HPIPE_SMAPLER_OFFSET; in mvebu_cp110_comphy_sata_power_on()
522 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
526 data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
527 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
531 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
532 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_sata_power_on()
536 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in mvebu_cp110_comphy_sata_power_on()
538 data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
539 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
543 data = sata_static_values->g3_ffe_cap_sel << in mvebu_cp110_comphy_sata_power_on()
546 data |= sata_static_values->g3_ffe_res_sel << in mvebu_cp110_comphy_sata_power_on()
549 data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
551 data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
553 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
554 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
558 data = sata_static_values->g3_dfe_res << HPIPE_G3_DFE_RES_OFFSET; in mvebu_cp110_comphy_sata_power_on()
559 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
563 data = sata_static_values->align90 << HPIPE_OS_PH_OFFSET_OFFSET; in mvebu_cp110_comphy_sata_power_on()
565 data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
567 data |= 0x0 << HPIPE_OS_PH_VALID_OFFSET; in mvebu_cp110_comphy_sata_power_on()
568 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
570 data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; in mvebu_cp110_comphy_sata_power_on()
571 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
573 data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; in mvebu_cp110_comphy_sata_power_on()
574 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
578 data = sata_static_values->g1_amp << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; in mvebu_cp110_comphy_sata_power_on()
580 data |= sata_static_values->g1_tx_amp_adj << in mvebu_cp110_comphy_sata_power_on()
583 data |= sata_static_values->g1_emph << in mvebu_cp110_comphy_sata_power_on()
586 data |= sata_static_values->g1_emph_en << in mvebu_cp110_comphy_sata_power_on()
588 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
592 data = sata_static_values->g1_tx_emph_en << in mvebu_cp110_comphy_sata_power_on()
595 data |= sata_static_values->g1_tx_emph << in mvebu_cp110_comphy_sata_power_on()
597 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
601 data = sata_static_values->g2_amp << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; in mvebu_cp110_comphy_sata_power_on()
603 data |= sata_static_values->g2_tx_amp_adj << in mvebu_cp110_comphy_sata_power_on()
606 data |= sata_static_values->g2_emph << in mvebu_cp110_comphy_sata_power_on()
609 data |= sata_static_values->g2_emph_en << in mvebu_cp110_comphy_sata_power_on()
611 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
615 data = sata_static_values->g2_tx_emph_en << in mvebu_cp110_comphy_sata_power_on()
618 data |= sata_static_values->g2_tx_emph << in mvebu_cp110_comphy_sata_power_on()
620 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
624 data = sata_static_values->g3_amp << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; in mvebu_cp110_comphy_sata_power_on()
626 data |= sata_static_values->g3_tx_amp_adj << in mvebu_cp110_comphy_sata_power_on()
629 data |= sata_static_values->g3_emph << in mvebu_cp110_comphy_sata_power_on()
632 data |= sata_static_values->g3_emph_en << in mvebu_cp110_comphy_sata_power_on()
635 data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; in mvebu_cp110_comphy_sata_power_on()
637 data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; in mvebu_cp110_comphy_sata_power_on()
638 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
642 data = sata_static_values->g3_tx_emph_en << in mvebu_cp110_comphy_sata_power_on()
645 data |= sata_static_values->g3_tx_emph << in mvebu_cp110_comphy_sata_power_on()
647 reg_set(hpipe_addr + HPIPE_G3_SET_2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
651 data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; in mvebu_cp110_comphy_sata_power_on()
652 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in mvebu_cp110_comphy_sata_power_on()
683 uint32_t mask, data, sgmii_speed = COMPHY_GET_SPEED(comphy_mode); in mvebu_cp110_comphy_sgmii_power_on() local
702 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
704 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
705 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
709 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
715 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
716 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
719 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
720 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
728 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
730 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
732 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
733 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
737 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
739 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
741 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
742 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
746 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
748 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
749 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
758 data = 0 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
759 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
765 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
766 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
769 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
771 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
772 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
775 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
776 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
779 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
781 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
782 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
785 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
786 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
798 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
800 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
802 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
803 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
811 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
812 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
816 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in mvebu_cp110_comphy_sgmii_power_on()
817 mask = data; in mvebu_cp110_comphy_sgmii_power_on()
818 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT); in mvebu_cp110_comphy_sgmii_power_on()
819 if (data != 0) { in mvebu_cp110_comphy_sgmii_power_on()
827 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
829 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in mvebu_cp110_comphy_sgmii_power_on()
830 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_sgmii_power_on()
843 uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode); in mvebu_cp110_comphy_xfi_power_on() local
895 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
897 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
898 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
904 data = 0 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
905 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
909 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
911 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
913 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
915 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
917 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
919 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
920 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
924 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
926 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
928 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
929 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
932 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
934 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
936 data |= 0x1 << SD_EXTERNAL_CONFIG1_TX_IDLE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
937 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
947 data = 0x0U; in mvebu_cp110_comphy_xfi_power_on()
948 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
954 data = (speed == COMPHY_SPEED_5_15625G) ? in mvebu_cp110_comphy_xfi_power_on()
958 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
959 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
962 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
964 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
965 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
968 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
969 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
972 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
974 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
975 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
978 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
979 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
984 data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
986 data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
988 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
990 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
993 data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
995 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1001 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1002 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1005 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1006 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1010 data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1013 data = xfi_static_values->g1_amp << in mvebu_cp110_comphy_xfi_power_on()
1016 data |= xfi_static_values->g1_emph << in mvebu_cp110_comphy_xfi_power_on()
1020 data |= xfi_static_values->g1_emph_en << in mvebu_cp110_comphy_xfi_power_on()
1023 data |= xfi_static_values->g1_tx_amp_adj << in mvebu_cp110_comphy_xfi_power_on()
1026 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1029 data = xfi_static_values->g1_tx_emph << in mvebu_cp110_comphy_xfi_power_on()
1032 data |= xfi_static_values->g1_tx_emph_en << in mvebu_cp110_comphy_xfi_power_on()
1034 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1037 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1039 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1040 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1043 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1045 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1046 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1049 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1050 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1054 data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1057 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1059 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1062 data |= xfi_static_values->g1_rx_selmupi << in mvebu_cp110_comphy_xfi_power_on()
1065 data |= xfi_static_values->g1_rx_selmupf << in mvebu_cp110_comphy_xfi_power_on()
1068 data |= xfi_static_values->g1_rx_selmufi << in mvebu_cp110_comphy_xfi_power_on()
1071 data |= xfi_static_values->g1_rx_selmuff << in mvebu_cp110_comphy_xfi_power_on()
1074 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1076 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1080 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1082 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1083 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1087 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1088 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1091 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1095 data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1097 data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1099 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1100 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1103 data |= xfi_static_values->g1_ffe_cap_sel << in mvebu_cp110_comphy_xfi_power_on()
1106 data |= xfi_static_values->g1_ffe_res_sel << in mvebu_cp110_comphy_xfi_power_on()
1109 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1110 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1114 data = 1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1117 data, mask); in mvebu_cp110_comphy_xfi_power_on()
1121 data = xfi_static_values->align90 << HPIPE_CAL_OS_PH_EXT_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1124 data, mask); in mvebu_cp110_comphy_xfi_power_on()
1128 data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1129 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1133 data = xfi_static_values->g1_dfe_res << in mvebu_cp110_comphy_xfi_power_on()
1135 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1140 data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1141 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1145 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1146 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1150 data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1151 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1155 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1156 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1160 data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1162 data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1163 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1167 data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1168 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1172 data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1173 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1177 data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1178 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1182 data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1184 data |= 0x1 << HPIPE_SMAPLER_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1185 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1187 data = 0x0 << HPIPE_SMAPLER_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1188 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1192 data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1193 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1198 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1200 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1202 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1203 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1207 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in mvebu_cp110_comphy_xfi_power_on()
1209 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1210 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_xfi_power_on()
1212 if (data != 0) { in mvebu_cp110_comphy_xfi_power_on()
1213 if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK) in mvebu_cp110_comphy_xfi_power_on()
1215 if (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK) in mvebu_cp110_comphy_xfi_power_on()
1223 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1224 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1228 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in mvebu_cp110_comphy_xfi_power_on()
1229 mask = data; in mvebu_cp110_comphy_xfi_power_on()
1230 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT); in mvebu_cp110_comphy_xfi_power_on()
1231 if (data != 0) { in mvebu_cp110_comphy_xfi_power_on()
1239 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1241 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in mvebu_cp110_comphy_xfi_power_on()
1242 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_xfi_power_on()
1245 data = mmio_read_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index)); in mvebu_cp110_comphy_xfi_power_on()
1246 data |= COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE; in mvebu_cp110_comphy_xfi_power_on()
1247 mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data); in mvebu_cp110_comphy_xfi_power_on()
1249 data &= ~COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE; in mvebu_cp110_comphy_xfi_power_on()
1250 mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data); in mvebu_cp110_comphy_xfi_power_on()
1261 uint32_t reg, mask, data, pcie_width; in mvebu_cp110_comphy_pcie_power_on() local
1336 data = 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1339 data, mask); in mvebu_cp110_comphy_pcie_power_on()
1341 data = 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1343 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1352 data = DFX_DEV_GEN_PCIE_CLK_SRC_MUX << in mvebu_cp110_comphy_pcie_power_on()
1356 DFX_DEV_GEN_CTRL12_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1362 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1364 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1366 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1368 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1370 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1371 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1375 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1377 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1378 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1386 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1389 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1392 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1395 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1396 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1398 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1401 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1403 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1406 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1409 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1416 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1417 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1419 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1422 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1424 data = 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1426 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1428 data = 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1430 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1434 data = 0; in mvebu_cp110_comphy_pcie_power_on()
1438 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1442 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1445 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1449 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1453 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1456 data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1457 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1461 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1465 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1469 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1470 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1475 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1476 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1489 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1492 data |= 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1495 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1496 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1500 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1503 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1504 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1508 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1511 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1514 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1515 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1519 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1522 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1523 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1528 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1530 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1532 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1533 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1537 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1539 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1541 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1543 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1544 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1548 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1549 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1553 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1554 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1559 data = 0; in mvebu_cp110_comphy_pcie_power_on()
1560 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1564 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1565 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1569 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1570 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1574 data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1575 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1579 data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1582 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1585 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1586 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1590 data = 0x1 << HPIPE_SMAPLER_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1591 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1597 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1599 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1600 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1604 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1605 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1609 data = 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1611 data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1613 data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1615 data |= 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1616 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1619 data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1620 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1624 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1626 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1628 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1629 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1633 data = 0x3 << HPIPE_G2_DFE_RES_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1634 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1638 data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1639 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1643 data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1644 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1648 data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1649 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1653 data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1655 data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; in mvebu_cp110_comphy_pcie_power_on()
1657 data |= 0x6 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1658 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1661 data = 0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET; in mvebu_cp110_comphy_pcie_power_on()
1662 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG2_REG, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1674 data = 0x0; in mvebu_cp110_comphy_pcie_power_on()
1679 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask); in mvebu_cp110_comphy_pcie_power_on()
1707 data = (COMPHY_LANE0 << in mvebu_cp110_comphy_pcie_power_on()
1713 data = (COMPHY_LANE0 << in mvebu_cp110_comphy_pcie_power_on()
1724 data, mask); in mvebu_cp110_comphy_pcie_power_on()
1733 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; in mvebu_cp110_comphy_pcie_power_on()
1734 mask = data; in mvebu_cp110_comphy_pcie_power_on()
1735 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_pcie_power_on()
1738 if (data) { in mvebu_cp110_comphy_pcie_power_on()
1754 uint32_t mask, data; in mvebu_cp110_comphy_rxaui_power_on() local
1771 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1773 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1774 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1789 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1791 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1793 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1795 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1797 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1799 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1801 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1802 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1806 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1808 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1810 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1811 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1814 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1816 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1817 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1830 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1832 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1833 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1839 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1841 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1842 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1863 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1865 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1867 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1868 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1871 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1873 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1874 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1878 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1879 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1884 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1886 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1888 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1889 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1894 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in mvebu_cp110_comphy_rxaui_power_on()
1896 mask = data; in mvebu_cp110_comphy_rxaui_power_on()
1897 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT); in mvebu_cp110_comphy_rxaui_power_on()
1898 if (data != 0) { in mvebu_cp110_comphy_rxaui_power_on()
1900 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in mvebu_cp110_comphy_rxaui_power_on()
1902 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in mvebu_cp110_comphy_rxaui_power_on()
1903 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in mvebu_cp110_comphy_rxaui_power_on()
1914 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in mvebu_cp110_comphy_rxaui_power_on()
1915 mask = data; in mvebu_cp110_comphy_rxaui_power_on()
1916 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT); in mvebu_cp110_comphy_rxaui_power_on()
1917 if (data != 0) { in mvebu_cp110_comphy_rxaui_power_on()
1919 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in mvebu_cp110_comphy_rxaui_power_on()
1927 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1929 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in mvebu_cp110_comphy_rxaui_power_on()
1930 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_rxaui_power_on()
1941 uint32_t mask, data; in mvebu_cp110_comphy_usb3_power_on() local
1965 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1967 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1969 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1971 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1973 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1974 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1978 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1980 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1981 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
1990 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1993 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1996 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
1999 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
2000 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2011 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
2014 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
2015 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2048 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
2051 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
2054 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
2055 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2058 data = 0x1f << HPIPE_G2_TX_SSC_AMP_OFFSET; in mvebu_cp110_comphy_usb3_power_on()
2059 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask); in mvebu_cp110_comphy_usb3_power_on()
2072 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; in mvebu_cp110_comphy_usb3_power_on()
2073 mask = data; in mvebu_cp110_comphy_usb3_power_on()
2074 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT); in mvebu_cp110_comphy_usb3_power_on()
2075 if (data != 0) { in mvebu_cp110_comphy_usb3_power_on()
2077 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); in mvebu_cp110_comphy_usb3_power_on()
2090 uint32_t mask, data; in rx_pre_train() local
2098 data = (0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF); in rx_pre_train()
2100 data |= (0x0 << HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF); in rx_pre_train()
2101 reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask); in rx_pre_train()
2105 data = (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF); in rx_pre_train()
2107 data |= (0x0 << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF); in rx_pre_train()
2108 reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask); in rx_pre_train()
2111 data = (0x1 << HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF); in rx_pre_train()
2112 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask); in rx_pre_train()
2115 data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF); in rx_pre_train()
2116 reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask); in rx_pre_train()
2119 data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF); in rx_pre_train()
2120 reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask); in rx_pre_train()
2123 data = (0x0 << HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET); in rx_pre_train()
2124 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in rx_pre_train()
2127 data = (0x38 << HPIPE_TRX_REG1_SUMFTAP_EN_OFF); in rx_pre_train()
2129 data |= (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF); in rx_pre_train()
2130 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask); in rx_pre_train()
2136 uint32_t mask, data, timeout; in mvebu_cp110_comphy_xfi_rx_training() local
2155 data = 0 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2156 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2160 data = 0 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2162 data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2166 data = 0 << HPIPE_DFE_RES_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2167 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2172 data = 0x1 << HPIPE_TRX_RX_TRAIN_EN_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2173 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2181 data = mmio_read_32(hpipe_addr + HPIPE_INTERRUPT_1_REGISTER); in mvebu_cp110_comphy_xfi_rx_training()
2182 if (data & mask) in mvebu_cp110_comphy_xfi_rx_training()
2189 hpipe_addr + HPIPE_INTERRUPT_1_REGISTER, data); in mvebu_cp110_comphy_xfi_rx_training()
2191 if (timeout == 0 || data & HPIPE_TRX_TRAIN_TIME_OUT_INT_MASK) { in mvebu_cp110_comphy_xfi_rx_training()
2196 if (data & HPIPE_TRX_TRAIN_FAILED_MASK) { in mvebu_cp110_comphy_xfi_rx_training()
2202 data = 0x0 << HPIPE_TRX_RX_TRAIN_EN_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2203 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2242 data = g1_ffe_res_sel << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2243 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2247 data = g1_ffe_cap_sel << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2248 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2254 data = 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2255 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2259 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2260 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2264 data = g1_dfe_res << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; in mvebu_cp110_comphy_xfi_rx_training()
2265 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in mvebu_cp110_comphy_xfi_rx_training()
2303 uint32_t mask, data; in mvebu_cp110_comphy_ap_power_on() local
2314 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in mvebu_cp110_comphy_ap_power_on()
2316 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in mvebu_cp110_comphy_ap_power_on()
2317 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_ap_power_on()
2343 uint32_t mask, data; in mvebu_cp110_comphy_digital_reset() local
2355 data = ((command == COMPHY_COMMAND_DIGITAL_PWR_OFF) ? in mvebu_cp110_comphy_digital_reset()
2357 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_digital_reset()
2433 uint32_t mask, data; in mvebu_cp110_comphy_power_off() local
2460 data = mmio_read_32(comphy_base + in mvebu_cp110_comphy_power_off()
2462 data >>= (COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index); in mvebu_cp110_comphy_power_off()
2463 data &= COMMON_SELECTOR_COMPHY_MASK; in mvebu_cp110_comphy_power_off()
2464 if (data == COMMON_SELECTOR_PIPE_COMPHY_PCIE) in mvebu_cp110_comphy_power_off()
2482 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in mvebu_cp110_comphy_power_off()
2484 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in mvebu_cp110_comphy_power_off()
2486 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in mvebu_cp110_comphy_power_off()
2487 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in mvebu_cp110_comphy_power_off()
2496 data = mmio_read_32(SYS_CTRL_FROM_COMPHY_ADDR(comphy_base) + in mvebu_cp110_comphy_power_off()
2500 data &= ~PCIE_MAC_RESET_MASK_PORT0; in mvebu_cp110_comphy_power_off()
2503 data &= ~PCIE_MAC_RESET_MASK_PORT1; in mvebu_cp110_comphy_power_off()
2506 data &= ~PCIE_MAC_RESET_MASK_PORT2; in mvebu_cp110_comphy_power_off()
2511 SYS_CTRL_UINIT_SOFT_RESET_REG, data); in mvebu_cp110_comphy_power_off()
2516 data = 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in mvebu_cp110_comphy_power_off()
2518 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in mvebu_cp110_comphy_power_off()
2519 reg_set(comphy_ip_addr + COMMON_PHY_CFG1_REG, data, mask); in mvebu_cp110_comphy_power_off()