Lines Matching refs:COMPHY_SD_ADDR
31 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000) macro
396 sd_ip_addr = COMPHY_SD_ADDR; in mvebu_a3700_comphy_sgmii_power_on()
825 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR, in mvebu_a3700_comphy_pcie_power_on()
829 reg_set16(CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR, in mvebu_a3700_comphy_pcie_power_on()
833 reg_set16(MISC_CTRL1_ADDR(PCIE) + COMPHY_SD_ADDR, in mvebu_a3700_comphy_pcie_power_on()
837 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR, in mvebu_a3700_comphy_pcie_power_on()
843 reg_set16(IDLE_SYNC_EN_ADDR(PCIE) + COMPHY_SD_ADDR, in mvebu_a3700_comphy_pcie_power_on()
847 reg_set16(MISC_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, in mvebu_a3700_comphy_pcie_power_on()
866 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, in mvebu_a3700_comphy_pcie_power_on()
872 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, in mvebu_a3700_comphy_pcie_power_on()
884 reg_set16(SYNC_PATTERN_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); in mvebu_a3700_comphy_pcie_power_on()
889 reg_set16(RST_CLK_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask); in mvebu_a3700_comphy_pcie_power_on()
894 ret = polling_with_timeout(LANE_STAT1_ADDR(PCIE) + COMPHY_SD_ADDR, in mvebu_a3700_comphy_pcie_power_on()